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- Tasks: Create and implement test plans for complex interconnectivity IPs in cutting-edge technology.
- Company: Join a leading tech firm in Cambridge with a hybrid work model.
- Benefits: Competitive salary, flexible working options, and opportunities for professional growth.
- Why this job: Shape the future of technology while collaborating with top engineers in the field.
- Qualifications: 8+ years in hardware verification with expertise in UVM/SystemVerilog and EDA tools.
- Other info: Dynamic team environment with a focus on innovation and problem-solving.
The predicted salary is between 48000 - 72000 £ per year.
Location: Cambridge, England, United Kingdom (Hybrid possible inside the UK)
About the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions.
Responsibilities:
- Collaborate with design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems.
- Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards.
- Collaborate with software teams to define and implement configurable testbenches.
- Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.
Qualifications:
- BS/MS in Electrical Engineering, Computer Engineering or Computer Science.
- 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification.
- Proficiency in Verilog, SystemVerilog.
- Familiarity with industry-standard EDA tools for simulation and debug.
- Deep experience with UVM-based testbenches.
- Experience with modern programming languages like Python.
- Knowledge of ARM AMBA protocols such as AXI, APB, and AHBUnderstanding of ARM CHI protocol is a plus.
- Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs.
- Experience with formal verification techniques, emulation platforms is a plus.
- Excellent problem-solving skills and attention to detail.
- Strong communication and collaboration skills.
Senior Design Verification Engineer in Cambridge employer: Baya Systems
Contact Detail:
Baya Systems Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Senior Design Verification Engineer in Cambridge
✨Tip Number 1
Network like a pro! Reach out to your connections in the industry, attend meetups, and engage in online forums. You never know who might have the inside scoop on job openings or can refer you directly.
✨Tip Number 2
Show off your skills! Create a portfolio showcasing your best work, especially any testbenches or verification projects you've tackled. This will give potential employers a taste of what you can bring to the table.
✨Tip Number 3
Prepare for interviews by brushing up on your technical knowledge and problem-solving skills. Practice common interview questions related to design verification and be ready to discuss your past experiences in detail.
✨Tip Number 4
Don't forget to apply through our website! We love seeing candidates who are genuinely interested in joining our team. Plus, it makes it easier for us to keep track of your application and get back to you quickly.
We think you need these skills to ace Senior Design Verification Engineer in Cambridge
Some tips for your application 🫡
Tailor Your CV: Make sure your CV is tailored to the Senior Design Verification Engineer role. Highlight your experience with UVM/SystemVerilog and any relevant projects that showcase your skills in building testbenches and writing test sequences.
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you're passionate about design verification and how your background aligns with our needs. Don’t forget to mention specific technologies or methodologies you’ve worked with.
Showcase Your Problem-Solving Skills: In your application, give examples of how you've tackled complex verification challenges in the past. We love seeing candidates who can think critically and creatively to solve problems!
Apply Through Our Website: We encourage you to apply through our website for the best chance of getting noticed. It’s super easy, and you’ll be able to keep track of your application status directly!
How to prepare for a job interview at Baya Systems
✨Know Your Stuff
Make sure you brush up on your knowledge of UVM, SystemVerilog, and the ARM AMBA protocols. Be ready to discuss your hands-on experience with block-level and SOC-level verification. The more specific examples you can provide about your past projects, the better!
✨Showcase Your Collaboration Skills
Since this role involves working closely with design and software teams, be prepared to share examples of how you've successfully collaborated in the past. Highlight any experiences where you’ve created test plans or debugged issues as part of a team.
✨Prepare for Technical Questions
Expect some technical questions that will test your problem-solving skills. Brush up on your knowledge of EDA tools and be ready to explain how you would approach debugging a complex issue. Practising common scenarios can help you feel more confident.
✨Ask Insightful Questions
At the end of the interview, don’t forget to ask questions! Inquire about the company’s technology portfolio or the challenges they face in verification. This shows your genuine interest in the role and helps you assess if it’s the right fit for you.
