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- Tasks: Build cutting-edge formal verification environments to find bugs and prove correctness in designs.
- Company: Axiomise is a leading formal verification training and consulting company in the semiconductor industry.
- Benefits: Enjoy flexible working hours, a generous benefits package, and opportunities for personal growth.
- Why this job: Join a collaborative culture where innovation thrives and your ideas can make a real impact.
- Qualifications: Bachelor/Masters/Doctorate in EEE/ECE/CS/Maths with skills in Verilog/VHDL and scripting languages.
- Other info: Entry-level position with a supportive team and potential for publishing papers and filing patents.
The predicted salary is between 30000 - 42000 £ per year.
Axiomise is the world’s only formal verification (FV) training, consulting, services and custom solutions company. In its 8th year, we have delivered training to over a hundred engineers globally and provided our consulting & services to some of the best names in the semiconductor industry. We designed the industry’s first and only vendor-neutral fully automated RISC-V formal verification app that has been used to find bugs in pre-existing processors and exhaustively prove bug absence. We love formal methods, and we use them day and night to sign-off designs, so our customers do not leave bugs in silicon.
We do not have a hierarchical structure so you will learn fast. We focus on innovation and every individual is invited to build cool new solutions, publish papers, file patents, and work live with customers. We are an equal opportunity employer, having a representation of 11 nationalities and 41% female employees. We are looking for bright spirited individuals with a positive can-do attitude. We often work on very challenging problems that are not always solvable within a 9-to-5 framework, so we expect our team to put in extra hours if needed. We welcome our engineering talent to also get involved in other areas of our business and we take pride that we are agile and can respond swiftly to our customer and employee needs.
We are looking to hire top-notch engineering talent for the UK. Your typical day job would involve building cutting-edge formal verification testbench environments to find bugs and build proofs of bug absence in SoCs containing processors, video/GPUs, networking, AI/ML designs. Formal verification is the only way to generate proofs of correctness and build proofs of bug absence. We train engineers in the best-known semiconductor names, and you can assume that we will provide you with the best FV training to get you started. All we expect from you is a passion for digital design, computer architecture and problem-solving. There is a substantial amount of hands-on work on formal verification of processors, GPU blocks, networking designs or AI/ML. The work will include building strategy, verification plans, testbenches and sign-off using the Axiomise six-dimensional coverage methodology. You are expected to be confident in Verilog/VHDL as well as fluent in SVA and Tcl/Perl/Python and Unix/Linux scripting.
Profile of a successful candidate:
- Education: Bachelor/Masters/Doctorate in EEE/ECE/CS/Maths
- Technical Skills: RISC-V/Arm/x86/MIPS SVA/PSL/Theorem proving Tcl/Python/Bash
- Soft Skills: Problem solving, Ownership, Autonomy, Team spirit
- Experience: 0-5 years
Once hired by us, the company offers compensation based on prevailing market rates and a generous package of benefits, such as:
- Company Pension
- Employee Assistance Programme
- Eye Test Vouchers
- Cycle to Work Scheme
- Employee Birthday Treat
- Employee Recognition Awards
- Employee Coffee Mornings
- Bonus System
- Potential to file patents, publish papers at top conferences
- Social and Well-Being Events
- Flexible Working Hours
Hiring process: As a process, our recruitment follows 3 stages: Math test, Technical interview, HR interview
Seniority level: Entry level
Employment type: Full-time
Job function: Quality Assurance
Industries: Semiconductor Manufacturing
Formal Verification Engineer employer: Axiomise
Contact Detail:
Axiomise Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Formal Verification Engineer
✨Tip Number 1
Familiarise yourself with formal verification concepts and tools. Since Axiomise focuses on cutting-edge formal verification, having a solid understanding of the principles behind it will help you stand out during interviews.
✨Tip Number 2
Brush up on your programming skills, especially in Verilog, VHDL, and scripting languages like Python and Tcl. Being able to demonstrate your coding proficiency can significantly boost your chances of landing the job.
✨Tip Number 3
Showcase your problem-solving abilities through practical examples. Be prepared to discuss specific challenges you've faced in previous projects and how you overcame them, as this aligns with Axiomise's focus on innovation and tackling complex problems.
✨Tip Number 4
Engage with the semiconductor community online. Join forums or attend webinars related to formal verification and semiconductor design. This not only expands your knowledge but also helps you network with professionals in the field, which could lead to valuable connections at Axiomise.
We think you need these skills to ace Formal Verification Engineer
Some tips for your application 🫡
Understand the Role: Before applying, make sure you fully understand the responsibilities of a Formal Verification Engineer. Familiarise yourself with formal verification concepts and the specific technologies mentioned in the job description, such as Verilog/VHDL, SVA, and various scripting languages.
Tailor Your CV: Craft your CV to highlight relevant skills and experiences that align with the job requirements. Emphasise your education in EEE/ECE/CS/Maths and any hands-on experience with formal verification or related projects. Use keywords from the job description to make your application stand out.
Write a Compelling Cover Letter: In your cover letter, express your passion for digital design and problem-solving. Mention why you are interested in Axiomise and how your background makes you a great fit for their innovative culture. Be sure to convey your enthusiasm for working on challenging problems.
Prepare for Assessments: Since the hiring process includes a math test and technical interview, brush up on your mathematical skills and relevant technical knowledge. Practice common interview questions related to formal verification and be ready to discuss your problem-solving approach.
How to prepare for a job interview at Axiomise
✨Brush Up on Your Technical Skills
Make sure you're well-versed in Verilog/VHDL, SVA, and the scripting languages mentioned in the job description. Be prepared to discuss your experience with these technologies and how you've applied them in past projects.
✨Show Your Problem-Solving Skills
Axiomise values candidates who can tackle challenging problems. Prepare examples from your academic or professional experience where you successfully solved complex issues, particularly in digital design or formal verification.
✨Demonstrate Your Passion for Formal Verification
Express your enthusiasm for formal methods and their application in the semiconductor industry. Discuss any relevant projects or coursework that highlight your interest and understanding of formal verification.
✨Prepare for the Math Test
Since the hiring process includes a math test, brush up on your mathematical skills, especially those relevant to computer science and engineering. Practice problems related to logic, algorithms, and proofs to ensure you're ready.
