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- Tasks: Build cutting-edge formal verification environments to find bugs and prove correctness in designs.
- Company: Axiomise is a leading formal verification training and consulting company in the semiconductor industry.
- Benefits: Enjoy flexible working hours, a generous benefits package, and opportunities for professional growth.
- Why this job: Join a collaborative culture focused on innovation and solving challenging problems with a diverse team.
- Qualifications: Bachelor/Masters/Doctorate in EEE/ECE/CS/Maths; skills in Verilog/VHDL, SVA, Tcl/Python required.
- Other info: Entry-level position with a supportive environment for learning and development.
The predicted salary is between 28800 - 48000 £ per year.
About us: Axiomise is the world’s only formal verification (FV) training, consulting, services and custom solutions company. In its 8th year, we have delivered training to over a hundred engineers globally and provided our consulting & services to some of the best names in the semiconductor industry. We designed the industry’s first and only vendor-neutral fully automated RISC-V formal verification app that has been used to find bugs in pre-existing processors and exhaustively prove bug absence. We love formal methods, and we use them day and night to sign-off designs, so our customers do not leave bugs in silicon.
Snapshot of our culture: We do not have a hierarchical structure so you will learn fast. We focus on innovation and every individual is invited to build cool new solutions, publish papers, file patents, and work live with customers. We are an equal opportunity employer, having a representation of 11 nationalities and 41% female employees. We are looking for bright spirited individuals with a positive can-do attitude. We often work on very challenging problems that are not always solvable within a 9-to-5 framework, so we expect our team to put in extra hours if needed. We welcome our engineering talent to also get involved in other areas of our business and we take pride that we are agile and can respond swiftly to our customer and employee needs.
About the Job: We are looking to hire top-notch engineering talent for the UK. Your typical day job would involve building cutting-edge formal verification testbench environments to find bugs and build proofs of bug absence in SoCs containing processors, video/GPUs, networking, AI/ML designs. Formal verification is the only way to generate proofs of correctness and build proofs of bug absence. We train engineers in the best-known semiconductor names, and you can assume that we will provide you with the best FV training to get you started. All we expect from you is a passion for digital design, computer architecture and problem-solving. There is a substantial amount of hands-on work on formal verification of processors, GPU blocks, networking designs or AI/ML. The work will include building strategy, verification plans, testbenches and sign-off using the Axiomise six-dimensional coverage methodology. You are expected to be confident in Verilog/VHDL as well as fluent in SVA and Tcl/Perl/Python and Unix/Linux scripting.
Profile of a successful candidate:
- Education: Bachelor/Masters/Doctorate in EEE/ECE/CS/Maths
- Technical Skills: RISC-V/Arm/x86/MIPS SVA/PSL/Theorem proving Tcl/Python/Bash
- Soft Skills: Problem solving, Ownership, Autonomy, Team spirit
- Experience: 0-5 years
Once hired by us, the company offers compensation based on prevailing market rates and a generous package of benefits, such as:
- Company Pension
- Employee Assistance Programme
- Eye Test Vouchers
- Cycle to Work Scheme
- Employee Birthday Treat
- Employee Recognition Awards
- Employee Coffee Mornings
- Bonus System
- Potential to file patents, publish papers at top conferences
- Social and Well-Being Events
- Flexible Working Hours
Hiring process: As a process, our recruitment follows 3 stages: Math test, Technical interview, HR interview.
Seniority level: Entry level
Employment type: Full-time
Job function: Quality Assurance
Industries: Semiconductor Manufacturing
Contact Detail:
Axiomise Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Formal Verification Engineer
✨Tip Number 1
Familiarise yourself with formal verification concepts and tools. Since Axiomise focuses on cutting-edge formal verification, having a solid understanding of the principles and methodologies will help you stand out during interviews.
✨Tip Number 2
Engage with the RISC-V community and explore relevant projects. Demonstrating your involvement in this area can showcase your passion for digital design and problem-solving, which aligns with Axiomise's values.
✨Tip Number 3
Brush up on your programming skills, especially in Verilog/VHDL and scripting languages like Python or Tcl. Being confident in these areas will not only prepare you for the technical interview but also show your readiness to tackle hands-on work.
✨Tip Number 4
Prepare for the math test by reviewing relevant topics such as logic, set theory, and combinatorial problems. A strong performance in this stage is crucial, as it sets the foundation for your technical capabilities in formal verification.
We think you need these skills to ace Formal Verification Engineer
Some tips for your application 🫡
Understand the Role: Before applying, make sure you fully understand the responsibilities of a Formal Verification Engineer. Familiarise yourself with formal verification concepts, tools, and methodologies mentioned in the job description.
Tailor Your CV: Highlight relevant skills and experiences in your CV that align with the job requirements. Emphasise your knowledge of Verilog/VHDL, SVA, and any experience with Tcl/Python/Bash scripting, as well as your educational background in EEE/ECE/CS/Maths.
Craft a Compelling Cover Letter: Write a cover letter that showcases your passion for digital design and problem-solving. Mention specific projects or experiences that demonstrate your skills in formal verification and your ability to work autonomously and collaboratively.
Prepare for Assessments: Since the hiring process includes a math test and technical interview, brush up on your mathematical skills and be ready to discuss your technical knowledge in detail. Practice common interview questions related to formal verification and semiconductor design.
How to prepare for a job interview at Axiomise
✨Brush Up on Your Technical Skills
Make sure you're well-versed in Verilog/VHDL, SVA, and the scripting languages mentioned in the job description. Be prepared to discuss your experience with these technologies and how you've applied them in past projects.
✨Show Your Passion for Problem-Solving
Axiomise values individuals who are passionate about digital design and problem-solving. Be ready to share examples of challenging problems you've tackled and how you approached finding solutions.
✨Demonstrate Team Spirit
Since Axiomise promotes a collaborative culture, highlight your experiences working in teams. Discuss how you contribute to team dynamics and support your colleagues in achieving common goals.
✨Prepare for the Math Test
As part of the hiring process, you'll need to take a math test. Brush up on relevant mathematical concepts and practice problems that may be similar to what you'll encounter during the test.
