Formal Verification Engineer

Overview

Your mission: We expect a passion for digital design, computer architecture and problem-solving.

There is a substantial amount of hands-on work on formal verification of processors, GPU blocks, networking designs or AI/ML. The work will include building strategy, verification plans, testbenches and sign-off using the Axiomise six-dimensional coverage methodology. You are expected to be confident in Verilog/VHDL as well as fluent in SVA and Tcl/Perl/Python and Unix/Linux scripting.

Responsibilities

• Independently executes formal verification activities for complex hardware designs, ensuring functional correctness, robustness, and quality before tape-out.
• Develops and optimizes properties, runs advanced formal verification techniques,Mentors junior engineers, and collaborates closely with design teams to achieve verification closure.
• Builds cutting-edge formal verification testbench environments to find bugs and build proofs of bug absence in SoCs containing processors, video/GPUs, networking, AI/ML designs.
• Formal verification is used to generate proofs of correctness and build proofs of bug absence.
• We train engineers with FV training to get started.

Profile Of a Successful Candidate

Education
Bachelors/Masters/Doctorate in EEE/ECE/CS/Maths/Physics

Technical Skills:
Linux/Unix Verilog/VHDL design Open-source projects in design/verification RISC-V/Arm/x86/MIPS SVA/PSL/Theorem proving Tcl/Python/Bash Analytical math skills Impeccable technical delivery

Soft Skills
Problem solving Ownership Autonomy Team spirit Attention to details

Language skills: English

Experience :
2-3 years of relevant design/verification experience 1-2 years of FV experience
at least 1 project experience where autonomously run small scale projects (<2>

Visa Sponsorship :
We provide sponsorship for exceptional candidates, upon conditional terms and conditions.

Why us?

Axiomise is the worlds only formal verification (FV) training, consulting, services and custom solutions company. Since 2017, we have delivered training to 100+ engineers globally and provided our consulting & services to FTSE 500 companies. We designed the industrys first and only vendor-neutral fully automated RISC-V formal verification app that has been used to find bugs in pre-existing processors and exhaustively prove bug absence. We love formal methods, and we use them day and night to sign-off designs, so our customers do not leave bugs in silicon.

Benefits

Company Pension Private Healthcare Employee Assistance Programme Eye Test vouchers Cycle to work scheme Employee Birthday treat (voucher & cake) Employee Recognition Awards Employee Coffee mornings Bonus System Potential to file patents, publish papers at top conferences Flexible working arrangements (including WFH)