Director - Hardware Engineering, AI Infrastructure Systems

About Us

Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years, we have raised a total of $370 million and have built a world-class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), both remotely from 18 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands. We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million. Our unwavering commitment to innovation has firmly established us as a global industry pioneer.

Position Overview

We are looking for an entrepreneurial, technically exceptional engineering leader to establish and run Axelera’s AI Infrastructure Systems division within the AI Integrated Systems (AIS) group. This is a new function, created to realize and deliver our next-generation accelerator silicon into datacenter-class form factors from PCIe accelerator cards and OAM-class modules to full 1U/2U rack systems and dense compute nodes targeting enterprise AI, sovereign cloud and HPC customers. You will build the team, shape the technical roadmap, and own end-to-end delivery of board- and system-level products for two strategic programmes. You will partner closely with the engineering leadership of the Embedded AI product line within AIS, System and Platform Architecture within R&D, the silicon organisation, the Voyager SDK/software group, and Axelera’s go-to-market teams serving hyperscalers, sovereign AI initiatives and the European HPC ecosystem. This role is deeply hands-on, owning implementation, validation, and delivery of platform systems. You will review schematics and layouts, challenge power and thermal budgets, shape the BMC and platform-firmware stack, and walk the lab floor during bring-up. Strategic leadership without technical depth will not work here.

Key responsibilities:

• Build the Infrastructure Systems engineering team from the ground up: hire, structure and mentor a multidisciplinary organisation covering hardware architecture, PCB design, power/thermal/mechanical engineering, firmware and platform validation with in-house and 3rd-party resources.
• Define the technical roadmap for the division’s board- and system-level server products—PCIe Gen6/CXL accelerator cards, OAM modules and UBB baseboards, and full 1U/2U rack systems, evolving toward rack-scale solutions including networking fabric and storage architecture—aligned with the next-generation system and silicon roadmap.
• Serve as the technical authority across system implementation, including schematics, PCB stack-ups, high-speed signaling (PCIe Gen5/6, CXL, high-speed SerDes), enterprise memory, power delivery and VRM design, SI/PI methodology, and mechanical/thermal integration.
• Own end-to-end execution from concept through design reviews, bring-up, validation, reliability qualification, DFM/DFT/DFR and mass-production readiness, including NPI and ramp with tier-1 CMs and ODMs. Make the build-vs-partner call on each program leading designs in-house where it differentiates, and co-designing with ODM partners where time-to-market or scale demands it.
• Drive datacenter-grade platform engineering: BMC-based management, Redfish/IPMI, UEFI/BIOS firmware, secure boot and root-of-trust, platform firmware resilience, enterprise RAS features, and out-of-band telemetry.
• Lead the thermal and mechanical strategy for high-power accelerator platforms, including air-cooled rack designs and, where appropriate, direct liquid cooling (DLC) and immersion-ready variants.
• Partner with the Embedded AI engineering leadership within AIS to align board and system-level execution across the two product lines, sharing reference designs, validation assets and CM/ODM relationships wherever it accelerates both streams.
• Collaborate with Platform Architecture, product management, silicon, SDK and software teams to refine and realize platform requirements (e.g. memory topology, interconnect, power states, telemetry) so that the server products showcase the accelerator’s capabilities at rack and cluster scale.
• Engage directly with strategic customers, system integrators and ecosystem partners (hyperscalers, sovereign cloud operators, HPC centres, OEMs/ODMs) to shape requirements and win design-ins.
• Define and enforce engineering processes, documentation standards, validation methodologies and quality gates for the new division, mapped to Axelera’s NPD framework.
• Identify and mitigate technical risks, resolve engineering escalations, and drive debugging and root-cause analysis during development, qualification and early production.
• Own the division’s engineering budget, CAPEX, external engineering spend and vendor relationships.

Qualifications:

• 15+ years in hardware engineering for complex electronics products, with at least 5 years in senior leadership roles running multidisciplinary teams.
• Proven track record of shipping datacenter- or server-class compute hardware into volume production: accelerator cards, OAM modules, UBB baseboards, GPU/xPU-class server platforms, compute nodes or rack-level systems.
• Deep expertise in high-speed interfaces (PCIe Gen4/5/6, CXL, high-speed SerDes), server memory, high-current power delivery and VRM design, and high-density PCB layout with rigorous SI/PI methodology.
• Experience with BMC-based platform management, Redfish/IPMI, UEFI/BIOS or equivalent firmware stacks, secure boot/root-of-trust, and enterprise RAS features.
• Working knowledge of datacenter thermal and mechanical design: air-cooled 1U/2U chassis, direct liquid cooling and/or immersion-ready platforms, and rack power delivery at 12V, 48V and OCP power-shelf level.
• Familiarity with datacenter and AI infrastructure compliance and with PCIe and OCP standards.
• Experience working with tier-1 CMs/ODMs on server-class products, including DFM, MP transfer, yield ramp and sustaining engineering.
• Hands-on ability to review schematics, layouts, simulation results and lab validation data and to make the call when the team is stuck.
• Strong strategic thinker, excellent communicator, skilled at decision-making in fast-moving environments, comfortable engaging at C-level with customers and partners.

Preference:

• Experience building or significantly scaling an engineering team is strongly preferred.
• Experience with AI accelerator platforms, GPUs or custom silicon in a datacenter context is a strong plus.
• Exposure to sovereign AI, EuroHPC, HPC or European defence/dual-use datacenter programmes is a plus.
• Fluent English required; additional European language is a plus.

Location

We offer a flexible working arrangement, with options to: Work from one of our Axelera AI offices (Florence and Milan in Italy, Amsterdam and Eindhoven in the Netherlands, Leuven in Belgium, Paris in France, Zurich in Switzerland, or Bristol in the United Kingdom) if you're already based in the vicinity. Work fully remotely from the US or any European country (incl. the UK) you are already in. Relocate with us and work from Amsterdam or Eindhoven in the Netherlands, or Bologna, Florence or Milan in Italy.

What we offer

This is your chance to shape and be part of a dynamic, fast-growing, international organisation. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares. An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team. At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.