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- Tasks: Craft and verify innovative designs for cutting-edge power management products.
- Company: Join Apple, a leader in technology and innovation.
- Benefits: Competitive salary, inclusive culture, and opportunities for growth.
- Why this job: Be part of a team that shapes the future of technology.
- Qualifications: Strong knowledge of SystemVerilog and UVM; relevant degree required.
- Other info: Diverse and dynamic work environment with a focus on collaboration.
The predicted salary is between 36000 - 60000 £ per year.
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a driven and highly committed Design Verification Engineer. As a member of our multifaceted group, you will have the unique opportunity to craft upcoming products that will delight and encourage millions of customers every day.
We are looking for a Design Verification Engineer in our team, who will enable bug‑free first silicon for our mixed‑signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities include all phases of pre‑silicon verification including establishing design verification methodology and test‑plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test‑writing, debug, coverage, sign‑off for RTL freeze and tape‑out.
In this role you will develop verification plans in coordination with design leads and architects. You’ll be responsible for building and maintaining verification test bench components and environments. Generate directed and constrained random tests. Run simulations and debug design and environment issues. Build functional coverage points, analyze coverage, and improve test environment to target coverage holes. Craft automated verification flows for block and chip level verification. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM/VVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure a flawless verification flow.
Minimum Qualifications
- Strong knowledge of SystemVerilog and UVM
- Experience developing scalable and portable test‑benches
- Experience with constrained random verification environments
- MS/BS in Computer Science or Electrical Engineering or equivalent
- Fluency in English language is required
Preferred Qualifications
- Experience defining coverage space, writing coverage model, analyzing results
- Experience with Assertion Based Verification
- Knowledge of Object Oriented Programming
- Experience in Formal Verification (Formal Linting, Formal connectivity, user property verification)
- Experience with Python, Perl or TCL
- Excellent communication and interpersonal skills combined with the ability to collaborate
- Basic knowledge of mixed signal verification
Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
At Apple, we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law.
Design Verification Engineer - Power Management (m/f/d) in Swindon employer: Apple
Contact Detail:
Apple Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Design Verification Engineer - Power Management (m/f/d) in Swindon
✨Tip Number 1
Network like a pro! Reach out to current employees at Apple or in the design verification field. A friendly chat can give you insider info and maybe even a referral, which can really boost your chances.
✨Tip Number 2
Show off your skills! Prepare a portfolio or a project that highlights your experience with SystemVerilog and UVM. When you get the chance to chat with recruiters or during interviews, having something tangible to discuss can set you apart.
✨Tip Number 3
Practice makes perfect! Brush up on your technical skills and be ready to tackle some coding challenges or problem-solving scenarios during interviews. The more prepared you are, the more confident you'll feel.
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you’re serious about joining the team at Apple.
We think you need these skills to ace Design Verification Engineer - Power Management (m/f/d) in Swindon
Some tips for your application 🫡
Tailor Your CV: Make sure your CV reflects the skills and experiences that match the Design Verification Engineer role. Highlight your knowledge of SystemVerilog, UVM, and any relevant projects you've worked on. We want to see how you can contribute to our team!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you're passionate about design verification and how your background aligns with our mission at Apple. Let us know what excites you about the role and how you can help us change the game.
Showcase Your Technical Skills: Don’t forget to mention your experience with test-bench development and simulation tools. We love seeing candidates who can demonstrate their technical prowess, so include specific examples of your work with hardware description languages and verification environments.
Apply Through Our Website: We encourage you to apply directly through our website for the best chance of getting noticed. It’s the easiest way for us to keep track of your application and ensure it reaches the right people. Good luck!
How to prepare for a job interview at Apple
✨Know Your Tech Inside Out
Make sure you brush up on your knowledge of SystemVerilog, UVM, and mixed-signal verification. Be ready to discuss how you've used these tools in past projects, as well as any challenges you've faced and how you overcame them.
✨Prepare for Scenario-Based Questions
Expect questions that ask you to solve specific design verification problems. Practice explaining your thought process clearly and logically, as this will showcase your problem-solving skills and technical expertise.
✨Show Off Your Collaboration Skills
Since the role involves working closely with Digital and Analog Design engineers, be prepared to share examples of how you've successfully collaborated in the past. Highlight your communication skills and how you handle feedback.
✨Demonstrate Your Passion for Innovation
Apple values creativity and innovation, so be ready to discuss how you approach challenges and think outside the box. Share any experiences where you’ve contributed to a project that pushed boundaries or improved processes.
