Experienced AMS Design Verification Engineer in London
Experienced AMS Design Verification Engineer

Experienced AMS Design Verification Engineer in London

London Full-Time 36000 - 60000 £ / year (est.) No home office possible
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At a Glance

  • Tasks: Craft innovative products and ensure bug-free designs in a dynamic team.
  • Company: Join Apple, a leader in technology and innovation.
  • Benefits: Competitive salary, inclusive culture, and opportunities for growth.
  • Why this job: Be part of a team that shapes the future of technology.
  • Qualifications: Experience in System Verilog and a passion for problem-solving.
  • Other info: Diverse environment with a commitment to inclusion and career development.

The predicted salary is between 36000 - 60000 £ per year.

At Apple, we work daily to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and creative Design Verification Engineer. As a member of our Advanced Technology group, you will have the rare and rewarding opportunity to craft upcoming products, which will delight and encourage millions of Apple's customers every single day.

This role is for a Design Verification Engineer who will enable bug-free first silicon for the mixed-signal designs in our NEW London team. The responsibilities include all phases of pre-silicon verification, including but not limited to: construction of verification environments, coding of test scenarios and assertions, and close collaboration with Analog and Digital Design engineers.

Responsibilities
  • Definition and design of self-checking verification environments for multi-layer systems using the SystemVerilog UVM library.
  • The responsibility spans from concept discussions, verification strategy definition and execution of the verification tasks to ensure bug-free tape-outs.
  • The AMS DV engineer goes beyond standard verification techniques and includes:
  • Performance-based analysis
  • Power related analysis and scenario design for early power estimation
  • Deliveries of tests for design and test engineering teams
  • Gate-level verification (power and timing)
  • Lab bring-up support

A significant part of the AMS DV team focuses on research and innovations to improve verification techniques and tools for mixed-signal systems in order to increase efficiency and quality. Looking forward and establishing cutting edge concepts and methods to support them are part of the AMS DV team's DNA.

Minimum Qualifications
  • Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)
  • Hands-on experience with constrained random verification environments
  • Basic design background in support of verification results analysis
  • Knowledge of Object Oriented Programming (OOP)
  • Proficiency in English language is required
Preferred Qualifications
  • Master's degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent
  • Experience in AI/ML is desired
  • Hands-on experience with Assertion Based Verification
  • Familiarity with system design using C++, Python or Verilog
  • Familiarity with FPGA emulation platforms

Experienced AMS Design Verification Engineer in London employer: Apple

At Apple, we pride ourselves on fostering a dynamic and inclusive work environment that encourages innovation and creativity. As part of our new London team, you'll have the unique opportunity to contribute to cutting-edge technology while enjoying a culture that values diversity and personal growth. With comprehensive benefits, ongoing professional development, and a commitment to work-life balance, Apple is an exceptional employer for those looking to make a meaningful impact in the tech industry.
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Contact Detail:

Apple Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Experienced AMS Design Verification Engineer in London

✨Tip Number 1

Network like a pro! Reach out to folks in the industry, especially those at Apple. Use LinkedIn to connect and engage with them. A friendly chat can sometimes lead to opportunities that aren’t even advertised!

✨Tip Number 2

Prepare for those interviews! Research common questions for Design Verification Engineers and practice your answers. We recommend doing mock interviews with friends or using online platforms to get comfortable.

✨Tip Number 3

Show off your skills! If you’ve worked on relevant projects, create a portfolio or GitHub repository showcasing your work. This gives you a chance to demonstrate your expertise beyond just your CV.

✨Tip Number 4

Apply through our website! It’s the best way to ensure your application gets seen. Plus, it shows you’re genuinely interested in being part of the Apple team. Don’t miss out on this opportunity!

We think you need these skills to ace Experienced AMS Design Verification Engineer in London

System Verilog
UVM (Universal Verification Methodology)
Constrained Random Verification
Object Oriented Programming (OOP)
Assertion Based Verification
C++
Python
Verilog
FPGA Emulation Platforms
Power Analysis
Performance-based Analysis
Verification Strategy Definition
Collaboration with Analog and Digital Design Engineers
Research and Innovation in Verification Techniques

Some tips for your application 🫡

Tailor Your CV: Make sure your CV is tailored to the role of Design Verification Engineer. Highlight your experience with System Verilog and UVM, and don’t forget to mention any hands-on projects that showcase your skills in verification environments.

Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about the role and how your background in electrical or computer engineering makes you a perfect fit for our team at Apple.

Showcase Your Problem-Solving Skills: In your application, give examples of challenges you've faced in previous roles and how you tackled them. We love forward-thinking individuals who can think outside the box and come up with innovative solutions!

Apply Through Our Website: Don’t forget to apply through our website! It’s the best way to ensure your application gets into the right hands. Plus, it shows us you’re serious about joining our amazing team.

How to prepare for a job interview at Apple

✨Know Your Tech Inside Out

Make sure you brush up on your knowledge of System Verilog and UVM. Be ready to discuss how you've used these tools in past projects, as well as any challenges you've faced and how you overcame them.

✨Showcase Your Problem-Solving Skills

Prepare to talk about specific instances where you've tackled complex verification issues. Highlight your approach to performance-based analysis and power-related scenarios, as this will demonstrate your ability to think critically and creatively.

✨Collaborate Like a Pro

Since the role involves close collaboration with Analog and Digital Design engineers, be ready to share examples of how you've successfully worked in teams. Discuss how you communicate technical concepts clearly and effectively to ensure everyone is on the same page.

✨Stay Ahead of the Curve

Research the latest trends in verification techniques and tools, especially for mixed-signal systems. Being able to discuss cutting-edge concepts and methods will show that you're not just keeping up but are also eager to innovate and improve processes.

Experienced AMS Design Verification Engineer in London
Apple
Location: London

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