AMS Design Verification Engineer – SystemVerilog/UVM

AMS Design Verification Engineer – SystemVerilog/UVM

Full-Time On-site
. Apple (UK) Limited

Apple in London invites a Design Verification Engineer to join the Advanced Technology group. You will drive pre-silicon verification for mixed-signal designs, building self-checking environments and writing tests and assertions in SystemVerilog/UVM.

You will collaborate with Analog and Digital Design teams to enable bug-free tape-outs, perform power and timing analyses, and push verification innovations in a fast-paced environment at Apple.

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AMS Design Verification Engineer – SystemVerilog/UVM employer: . Apple (UK) Limited

Apple is an exceptional employer, offering a dynamic work culture that fosters innovation and collaboration in the heart of the United Kingdom. With a strong emphasis on employee growth, you will have access to cutting-edge resources and mentorship opportunities, allowing you to shape the future of AI while working on impactful projects that reach millions globally. Join us to be part of a team that values creativity and excellence, making a meaningful difference in technology.

. Apple (UK) Limited

Contact Details:

. Apple (UK) Limited Recruitment Team