Experienced AMS Design Verification Engineer in London

Experienced AMS Design Verification Engineer in London

London Full-Time 36000 - 60000 € / year (est.) No home office possible
Apple Inc.

At a Glance

  • Tasks: Craft innovative products and ensure bug-free designs in a dynamic team environment.
  • Company: Join Apple, a leader in technology and innovation.
  • Benefits: Competitive salary, inclusive culture, and opportunities for personal growth.
  • Other info: Be part of a diverse team committed to inclusion and innovation.
  • Why this job: Make a real impact on products that delight millions of users worldwide.
  • Qualifications: Experience with System Verilog, UVM, and a passion for cutting-edge technology.

The predicted salary is between 36000 - 60000 € per year.

At Apple, we work daily to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and creative Design Verification Engineer. As a member of our Advanced Technology group, you will have the rare and rewarding opportunity to craft upcoming products, which will delight and encourage millions of Apple’s customers every single day. Do your life’s best work here at Apple!

This role is for a Design Verification Engineer who will enable bug‑free first silicon for the mixed‑signal designs in our NEW London team. The responsibilities include all phases of pre‑silicon verification, including but not limited to: construction of verification environments, coding of test scenarios and assertions, and close collaboration with Analog and Digital Design engineers.

Description

  • Definition and design of Self‑checking verification environments for multi‑layer systems using the SystemVerilog UVM library.
  • The responsibility spans from concept discussions, verification strategy definition and execution of the verification tasks to ensure bug‑free tape‑outs.
  • The AMS DV engineer goes beyond standard verification techniques and includes:
    • performance‑based analysis
    • power related analysis and scenario design for early power estimation
    • deliveries of tests for design and test engineering teams
    • gate‑level verification (power and timing)
    • lab bring‑up support

A significant part of the AMS DV team focuses on research and innovations to improve verification techniques and tools for mixed‑signal systems in order to increase efficiency and quality. Looking forward and establishing cutting‑edge concepts and methods to support them are part of the AMS DV team’s DNA.

Minimum Qualifications

  • Knowledge of System Verilog test‑bench language and UVM (Universal Verification Methodology)
  • Hands‑on experience with constrained random verification environments
  • Basic design background in support of verification results analysis
  • Knowledge of Object Oriented Programming (OOP)
  • Proficiency in English language is required

Preferred Qualifications

  • Master’s degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent
  • Experience in AI/ML is desired
  • Hands‑on experience with Assertion Based Verification
  • Familiarity with system design using C++, Python or Verilog
  • Familiarity with FPGA emulation platforms

Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.

At Apple, we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law.

Experienced AMS Design Verification Engineer in London employer: Apple Inc.

At Apple, we pride ourselves on fostering a dynamic and inclusive work environment where innovation thrives. As an Experienced AMS Design Verification Engineer in our new London team, you will not only contribute to cutting-edge technology but also enjoy exceptional employee growth opportunities, a collaborative culture, and the chance to work on groundbreaking projects that impact millions. Join us to be part of a company that values diversity and encourages you to do your life's best work.

Apple Inc.

Contact Detail:

Apple Inc. Recruiting Team

StudySmarter Expert Advice🤫

We think this is how you could land Experienced AMS Design Verification Engineer in London

Tip Number 1

Network like a pro! Reach out to current employees at Apple or in the AMS Design Verification field. A friendly chat can give you insider info and maybe even a referral, which can really boost your chances.

Tip Number 2

Prepare for those interviews by brushing up on your System Verilog and UVM knowledge. We all know that technical questions can be tough, so practice coding scenarios and explaining your thought process clearly.

Tip Number 3

Show off your passion for innovation! During interviews, share examples of how you've tackled complex verification challenges or contributed to improving processes. This will highlight your forward-thinking mindset.

Tip Number 4

Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you’re serious about joining the Apple team.

We think you need these skills to ace Experienced AMS Design Verification Engineer in London

System Verilog
UVM (Universal Verification Methodology)
Constrained Random Verification
Object Oriented Programming (OOP)
Assertion Based Verification
C++
Python

Some tips for your application 🫡

Tailor Your CV:Make sure your CV reflects the skills and experiences that match the job description. Highlight your knowledge of System Verilog and UVM, as well as any hands-on experience you've had with verification environments. We want to see how you can contribute to our team!

Craft a Compelling Cover Letter:Your cover letter is your chance to shine! Use it to explain why you're passionate about design verification and how your background makes you a great fit for our Advanced Technology group. Let us know what excites you about working at Apple!

Showcase Your Projects:If you've worked on relevant projects, whether in school or professionally, make sure to mention them. Discuss any innovative techniques or tools you've used in mixed-signal systems. We love seeing creativity and problem-solving in action!

Apply Through Our Website:We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensure it gets into the right hands. Plus, it shows us you're serious about joining our team!

How to prepare for a job interview at Apple Inc.

Know Your Stuff

Make sure you brush up on your knowledge of System Verilog and UVM. Be ready to discuss how you've used these tools in past projects, especially in creating self-checking verification environments. This will show that you’re not just familiar with the theory but have practical experience too.

Showcase Your Problem-Solving Skills

Prepare to talk about specific challenges you've faced in design verification and how you tackled them. Apple loves forward-thinking individuals, so highlight any innovative solutions you've implemented, especially those that improved efficiency or quality in mixed-signal systems.

Collaboration is Key

Since this role involves close collaboration with Analog and Digital Design engineers, be ready to share examples of how you've successfully worked in teams. Discuss how you communicate complex technical concepts to non-technical team members, as this will demonstrate your ability to work effectively in a diverse environment.

Stay Current with Trends

Familiarise yourself with the latest trends in AI/ML and how they can be applied to verification techniques. Being able to discuss these topics will not only impress your interviewers but also show that you're committed to continuous learning and innovation in your field.