Hardware Engineer (FPGA/ASIC) Internship, June-September
Design and test FPGA or ASIC systems using OCaml and Hardcaml, taking a hardware application from concept through RTL, testing, integration, and working design.
This internship combines hardware engineering with programming-language technology. Jane Street uses Hardcaml, an OCaml library for describing hardware in RTL, and interns work inside the same development environment used by its full-time hardware engineers.
What you will work on
The hardware team works on both FPGA and ASIC designs. Your project is chosen according to your background and is intended to give you exposure to Jane Street’s shared Hardcaml stack while targeting either an FPGA or ASIC platform. Interns are expected to take a hardware application from concept toward a working design, with most project work involving OCaml and Hardcaml for RTL design, testing, and integration.
Hardcaml is closely integrated with Jane Street’s internal software-development tools, so the internship also gives exposure to the libraries and infrastructure that support the firm’s broader engineering environment. Prior knowledge of Hardcaml or OCaml is not required.
What Jane Street expects
- Comfort programming in at least one software language.
- Experience with a hardware description or construction language such as VHDL, Verilog, Chisel, or PyMTL.
- Experience using FPGA or ASIC vendor tools such as Vivado, Quartus, Genus, or Innovus.
- At least one working FPGA or ASIC project from coursework, professional work, or a personal project.
- Interest in how programmable hardware is used in networking.
No finance, OCaml, or functional-programming background is required.
Details
Role information
Location London, United Kingdom
Job type Internship
Category Software Engineering
Company
New York, United States
Global quantitative trading and technology firm known for mathematical problem-solving, market making, and collaborative research-driven trading.
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