Senior FPGA Engineer - Hybrid (VHDL/Verilog)
Senior FPGA Engineer - Hybrid (VHDL/Verilog)

Senior FPGA Engineer - Hybrid (VHDL/Verilog)

Full-Time 184000 - 184000 £ / year (est.) Home office (partial)
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At a Glance

  • Tasks: Create robust VHDL designs and develop FPGA solutions.
  • Company: Join the American Society of Civil Engineers, a leader in civil engineering.
  • Benefits: Earn approximately £88 per hour with hybrid work and overtime opportunities.
  • Other info: Contact Lukas via WhatsApp for more details and apply today!
  • Why this job: Make an impact in engineering with cutting-edge FPGA technology.
  • Qualifications: 5+ years of FPGA experience with VHDL or Verilog required.

The predicted salary is between 184000 - 184000 £ per year.

The American Society of Civil Engineers is looking for a Senior / Principal FPGA Engineer based in the United Kingdom. The role involves creating robust VHDL-based designs and requires at least 5 years of FPGA development experience using VHDL or Verilog. Familiarity with Mentor Graphics tools and Xilinx design flows is essential. The position offers a hybrid work model, approximately £88 per hour, and includes overtime.

Interested candidates can apply directly or contact Lukas via WhatsApp or phone.

Senior FPGA Engineer - Hybrid (VHDL/Verilog) employer: American Society of Civil Engineers

The American Society of Civil Engineers is an exceptional employer, offering a dynamic work environment that fosters innovation and collaboration. With a hybrid work model, competitive pay, and opportunities for professional growth, employees are encouraged to develop their skills while contributing to impactful engineering projects. The supportive culture and commitment to employee well-being make it a rewarding place to advance your career in FPGA engineering.
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Contact Detail:

American Society of Civil Engineers Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Senior FPGA Engineer - Hybrid (VHDL/Verilog)

✨Tip Number 1

Network like a pro! Reach out to fellow engineers and industry contacts on LinkedIn. A personal connection can often get your foot in the door faster than a CV.

✨Tip Number 2

Show off your skills! Prepare a portfolio showcasing your VHDL/Verilog projects. Having tangible examples of your work can really impress during interviews.

✨Tip Number 3

Practice makes perfect! Brush up on common FPGA interview questions and technical challenges. The more prepared you are, the more confident you'll feel when it’s time to shine.

✨Tip Number 4

Apply through our website! We make it easy for you to submit your application directly, and it shows you're serious about joining our team. Don’t miss out!

We think you need these skills to ace Senior FPGA Engineer - Hybrid (VHDL/Verilog)

FPGA Development
VHDL
Verilog
Mentor Graphics Tools
Xilinx Design Flows
Robust Design Creation
Hybrid Work Model
Overtime Management

Some tips for your application 🫡

Tailor Your CV: Make sure your CV highlights your experience with VHDL and Verilog. We want to see how your skills match the job description, so don’t be shy about showcasing your FPGA development projects!

Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Tell us why you’re passionate about FPGA engineering and how your background makes you the perfect fit for this role. Keep it engaging and relevant to the position.

Showcase Relevant Tools Experience: Since familiarity with Mentor Graphics tools and Xilinx design flows is essential, make sure to mention any experience you have with these in your application. We love seeing candidates who are already familiar with the tools we use!

Apply Through Our Website: We encourage you to apply directly through our website for a smoother process. It helps us keep track of applications better and ensures you don’t miss out on any important updates!

How to prepare for a job interview at American Society of Civil Engineers

✨Know Your VHDL and Verilog Inside Out

Make sure you brush up on your VHDL and Verilog skills before the interview. Be prepared to discuss specific projects where you've used these languages, and think about the challenges you faced and how you overcame them.

✨Familiarise Yourself with Mentor Graphics and Xilinx

Since familiarity with Mentor Graphics tools and Xilinx design flows is essential, take some time to review these tools. If possible, practice using them or at least read up on their functionalities so you can confidently discuss your experience with them.

✨Prepare for Technical Questions

Expect technical questions that will test your FPGA development knowledge. We recommend reviewing common interview questions related to FPGA design and preparing clear, concise answers that showcase your expertise and problem-solving abilities.

✨Show Enthusiasm for Hybrid Work

As this role offers a hybrid work model, be ready to discuss how you manage your time and productivity in a flexible work environment. Share examples of how you've successfully worked remotely or in a hybrid setting in the past.

Senior FPGA Engineer - Hybrid (VHDL/Verilog)
American Society of Civil Engineers

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