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- Tasks: Design and verify cutting-edge analog and mixed-signal IP layouts for quantum technology.
- Company: Rapidly expanding deep-tech start-up in North London with a focus on innovation.
- Benefits: Competitive salary, equity options, flexible working, and a dynamic work environment.
- Why this job: Join a pioneering team and contribute to groundbreaking quantum technology projects.
- Qualifications: Strong Cadence skills, DRC and LVS expertise, and experience with deep sub-micron processes.
- Other info: Flexible working arrangements with at least 2 days in the office.
The predicted salary is between 60000 - 80000 £ per year.
A rapidly expanding deep-tech start-up in North London is seeking a Senior IC Layout Engineer to focus on designing and verifying analog and mixed-signal IP layout, capable of operating at cryogenic temperatures. The role allows for flexible working, ideally requiring at least 2 days in the office.
Candidates should possess:
- Strong Cadence skills
- Expertise in DRC and LVS
- Experience with deep sub-micron processes
A competitive salary and benefits, including a company share package, are offered.
Senior IC Layout Engineer for Quantum CMOS - Hybrid + Equity in London employer: American Society of Civil Engineers
Contact Detail:
American Society of Civil Engineers Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Senior IC Layout Engineer for Quantum CMOS - Hybrid + Equity in London
✨Tip Number 1
Network like a pro! Reach out to your connections in the industry, especially those who might know someone at the start-up. A personal introduction can make all the difference in getting your foot in the door.
✨Tip Number 2
Show off your skills! When you get the chance to chat with potential employers, be ready to discuss your experience with Cadence and deep sub-micron processes. Bring examples of your work to the conversation to really impress them.
✨Tip Number 3
Be flexible and adaptable! Since the role allows for hybrid working, highlight your ability to thrive in both office and remote settings. This shows you're ready to fit into their culture and workflow.
✨Tip Number 4
Apply through our website! We make it easy for you to submit your application directly, ensuring it gets seen by the right people. Plus, it shows you're serious about joining our team!
We think you need these skills to ace Senior IC Layout Engineer for Quantum CMOS - Hybrid + Equity in London
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience with Cadence, DRC, and LVS. We want to see how your skills align with the role, so don’t be shy about showcasing your expertise in deep sub-micron processes!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Tell us why you’re excited about working in a deep-tech start-up and how your background makes you the perfect fit for designing analog and mixed-signal IP layout.
Showcase Relevant Projects: If you've worked on projects that involved cryogenic temperatures or similar technologies, make sure to mention them. We love seeing real-world applications of your skills, so share those experiences with us!
Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you don’t miss out on any important updates from our team!
How to prepare for a job interview at American Society of Civil Engineers
✨Know Your Cadence Inside Out
Make sure you brush up on your Cadence skills before the interview. Be prepared to discuss specific projects where you've used Cadence for IC layout design, especially in analog and mixed-signal contexts. Highlight any challenges you faced and how you overcame them.
✨Understand Cryogenic Operations
Since the role involves designing for cryogenic temperatures, do some research on how temperature affects IC performance. Be ready to talk about any relevant experience you have with low-temperature electronics or how you would approach designing for such conditions.
✨Showcase Your DRC and LVS Expertise
Demonstrate your knowledge of Design Rule Checking (DRC) and Layout Versus Schematic (LVS) processes. Prepare examples of how you've successfully implemented these checks in past projects, and be ready to discuss the importance of these processes in ensuring high-quality layouts.
✨Be Ready for Technical Questions
Expect technical questions that test your understanding of deep sub-micron processes. Brush up on the latest trends and challenges in this area, and think about how your experience aligns with the company's needs. This will show that you're not just technically proficient but also engaged with the field.