At a Glance
- Tasks: Design cutting-edge communications tech for global connectivity and work on next-gen 5G networks.
- Company: Join a pioneering team shaping the future of satellite-based communications.
- Benefits: Competitive salary, flexible working options, and opportunities for professional growth.
- Other info: Collaborative environment with a focus on innovation and continuous improvement.
- Why this job: Make a real impact in the world of technology and enhance global mobile coverage.
- Qualifications: Strong experience in RTL design with Verilog/SystemVerilog and FPGA/ASIC development.
The predicted salary is between 63000 - 77000 £ per year.
We're looking for an experienced Senior Design Engineer to join a team developing cutting-edge communications technology that will help shape the future of global connectivity. This is an opportunity to work on next-generation 5G non-terrestrial networks developing digital hardware for satellite-based communications systems that will play a key role in delivering worldwide mobile coverage.
Working as part of a highly skilled engineering team, you'll be involved in the design and implementation of high-performance FPGA and ASIC solutions, taking products from architecture through to validation on the latest space-qualified hardware platforms.
Key responsibilities include:
- Translating system and algorithm requirements into RTL micro-architectures
- Designing and implementing RTL using Verilog/SystemVerilog for FPGA and ASIC targets
- Creating testbenches and supporting functional verification
- Deploying and validating designs on FPGA development platforms
- Optimising designs for performance, timing, power, and resource utilisation
- Producing high-quality technical documentation
- Collaborating across architecture, verification, physical implementation, and integration teams
- Contributing to continuous improvement of engineering processes and design methodologies
Skills & Experience
- Strong RTL design experience using Verilog and/or SystemVerilog
- Proven background developing complex FPGA and ASIC designs
- Experience optimising digital hardware for high-throughput signal or data processing
- Knowledge of synthesis, timing analysis, and power optimisation techniques
- Strong understanding of simulation and synthesis using industry-standard EDA tools
- Experience producing technical design documentation
- Excellent collaboration skills with multidisciplinary engineering teams
Desirable experience
- Communications or wireless signal processing
- Error correction, channel estimation, equalisation, or beamforming algorithms
- AMBA bus protocols
- UVM verification methodologies
- C++ or SystemC modelling
- High-speed interfaces such as PCIe or JESD
- Python or other scripting languages
- FPGA development using AMD/Xilinx devices
- ASIC backend flows and implementation tools
- Experience working within Agile or structured hardware development lifecycles
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