Field-Programmable Gate Arrays Engineer in Watford

FPGA Engineer

Location

Stevenage – Hybrid

Reporting to

Practice Lead

Company

Akkodis

Akkodis is a global leader in engineering, technology, and R&D, supporting clients with digital transformation, innovation, and advanced technology development.

As part of the Adecco Group, Akkodis employs over 50,000 engineers and digital specialists across 30 countries, working across areas including mobility, software services, robotics, simulations, cybersecurity, AI, and data analytics.

We are looking for an

FPGA Engineer to support the delivery of FPGA and So C-based firmware solutions for defence-related products.

This role will involve the full firmware development lifecycle, including requirements specification, architecture, design, implementation, verification, validation, certification support, and documentation.

Scope

You will work closely with systems, embedded software, hardware, and algorithm engineering teams to develop digital electronic systems using structured firmware development processes and industry-standard FPGA and So C development tools.

The role will suit an engineer with strong hands-on FPGA design capability, solid verification experience, and the ability to work effectively across cross-disciplinary engineering teams.

Role

As an FPGA Engineer, you will be responsible for developing FPGA and So C-based firmware solutions using modern digital design methodologies and tools.

Projects will involve RTL design, simulation, verification, integration with hardware, and support for safety, quality, and security-focused development processes.

Responsibilities

• Deliver firmware projects to agreed time, cost, and quality targets, with consideration for design reusability.
• Produce requirements specifications, architecture documentation, design documentation, implementation outputs, simulations, and verification evidence.
• Design and implement RTL logic for FPGA-based digital electronic systems.
• Integrate firmware designs with hardware platforms and wider system architectures.
• Support engineering processes including documentation, scripting, reporting, and process automation.
• Collaborate with systems, hardware, embedded software, and algorithm engineering teams.
• Recommend improvements to development processes, tools, and best practices.
• Ensure designs meet relevant safety, quality, and security standards, including DO-254, IEC 61508, IEC 62443, and ISO 26262 where applicable.
• Required Experience
• Experience developing RTL designs for digital electronics systems using VHDL.
• Experience working with Xilinx / AMD FPGA device architectures, or similar technologies such as Lattice.
• Experience with FPGA or So C implementation of algorithms developed in MATLAB / Simulink.
• Strong verification experience using OSVVM, UVVM, or UVM methodologies.
• Experience developing test bench architectures for FPGA verification.
• Familiarity with interface technologies such as AXI, PCIe, Ethernet, OCP, Wishbone, JESD204, Camera Link, or SMPTE.
• Experience using tools such as DOORS, Vivado, Model Sim, Diamond, Radiant, Vitis, or Propel.
• Ability to script using TCL or other scripting languages.
• Solid understanding of DO-254 processes.
• Experience working as part of an Integrated Product Team would be advantageous.
• Required Skills
• Strong FPGA / digital design engineering capability.
• Excellent communication skills, with the ability to work effectively across different technical teams and stakeholders.
• Strong analytical and problem-solving skills.
• Ability to work within structured engineering processes.
• Good documentation and reporting skills.
• Ability to support continuous improvement across tools, processes, and best practices.
• Technical or team leadership experience within small engineering teams would be beneficial.
• Required Education
• Degree in Electrical and Electronic Engineering, Electronics Engineering, or an equivalent electronics-related qualification.

Please get in touch to discuss the role in more detail or apply directly.