Principal Physical Design Engineer in Whitehall

Are you an experienced Physical Design Engineer looking for your next challenge? Aion Silicon is actively building a pipeline of talented engineers for future opportunities, and we'd love to hear from skilled professionals who are passionate about Physical Design. With design centres across the UK, Spain, Hyderabad, and Morocco, we offer the flexibility to base this role in any of our global locations.

Purpose of role

Full Chip Physical Design (PD) Expert is responsible for handling the entire physical implementation process of a complex System‑on‑Chip (SoC) or ASIC, from initial design handoff (RTL or netlist) to final sign‑off for manufacturing (GDSII). This role demands deep expertise across all aspects of the physical design flow and the ability to drive technical decisions at the chip level.

Responsibilities

• Display customer intimacy by demonstrating clear and customer focused communication, issue resolution & delivery beyond expectation.
• Take ownership and responsibility of the full‑chip activity assigned and deliver on day‑to‑day tasks.
• Actively participate in social engagements and create a culture of recognition to reward success and enhance collaboration.
• Mentor & coach PD team members working on blocks, training them on full‑chip PnR and sign‑off activities.
• Encourage a culture of appropriate delegation and knowledge sharing.
• Support hiring to address current and future skills gaps by actively participating in interviews.
• Coordinate and communicate with cross‑functional teams in defining Physical Design strategies/plans.
• Oversee and coach Physical Design Engineering Managers in developing their direct reports.
• Keep up to date with relevant engineering advances and ensure Aion Silicon remains at the forefront of state‑of‑the‑art technologies, methodologies and design processes.
• Represent Aion Silicon at universities, conferences and trade shows, and present technical papers.
• Integrate pad cells, ESD structures, and IO rings into the top‑level layout.
• Ensure signal and power bumps align correctly with pad locations and IO blocks.
• Plan and design power grids (PG), implement multi‑voltage domains and power gating, and perform IR drop and electromigration analysis and optimization.
• Define bump pitch, pattern and power/signal distribution; work with package and power integrity teams to align bump locations with package ball‑out and PDN requirements.
• Design and optimise multi‑level and multi‑domain clock trees, using techniques such as fishbone, H‑Tree, clock gating and mesh trees for better skew, latency and jitter.
• Optimise standard‑cell placement for timing and congestion; perform full‑chip and top‑level routing (global and detailed) and mitigate crosstalk, antenna and signal‑integrity issues.
• Own and manage full‑chip timing budgeting across hierarchical blocks; perform STA for setup/hold closure, timing ECOs, tapeout data preparation and documentation.
• Conduct DRC, LVS and ERC checks; perform parasitic extraction (RCX) and correlate with STA; sign‑off for IR/EM, noise and reliability.
• Generate and validate GDSII/OASIS data; ensure foundry rule compliance and provide tapeout handoff documentation.

Technical Skills

• 10+ years of physical design experience with proven hands‑on expertise in delivering three or more Full‑Chip Floorplanning & Integration.
• Experience in advanced technology nodes (7nm, 5nm, 3nm).
• Expertise with Synopsys (design compiler, ICC2, Fusion Compiler, ICV, Primetime, StarRC) and/or Cadence (Genus, Innovus, Tempus, Voltus) flows and Mentor Calibre flows.
• Ability to create floorplans from chip specification documents; hierarchical and flat design integration; block pin placement, channel planning and aspect‑ratio optimisation.

Qualifications

• Strong cross‑functional communication and leadership skills to drive chip‑level closure across RTL, STA, DFT and packaging teams.
• Proven track record of defining and conducting top‑level training for junior PD team members.
• Problem‑solving ability under pressure with focus on quality, ownership and timely delivery.
• Mentor and guide block‑level PD engineers on methodology and flow best practices.
• Review and approve block‑level physical design deliverables before integration.
• Lead debug sessions and technical discussions for closure issues.
• Ability to build trust through open and transparent communication.
• Reliable, dedicated and able to work under pressure; strong organisational, creative problem‑solving and time‑management skills.
• Positive mindset, demonstrates Aion Silicon values and embraces the company culture.