At a Glance
- Tasks: Lead the physical design of complex SoCs and ASICs, driving innovative strategies.
- Company: Join Aion Silicon, a leader in semiconductor innovation with a collaborative culture.
- Benefits: Competitive salary, hybrid work options, and opportunities for professional growth.
- Other info: Dynamic environment with exciting projects and excellent career advancement opportunities.
- Why this job: Make a real impact on cutting-edge technology and mentor future engineers.
- Qualifications: 10+ years in Physical Design with leadership experience and strong technical skills.
The predicted salary is between 60000 - 87100 £ per year.
Location: Global / Hybrid
Department: Engineering
Reports to: Physical Design Function Lead
Join Aion Silicon and Shape the Future of Semiconductor Innovation. At Aion Silicon, we are seeking an experienced Principal Physical Design Engineer to lead the physical implementation of complex, cutting-edge SoCs and ASICs. This is a senior technical leadership role for a recognised Full-Chip Physical Design expert who thrives on solving complex challenges, mentoring engineering teams, and driving successful tape-outs on advanced technology nodes. You will take ownership of the complete physical design flow, from RTL/netlist handoff through to final sign-off and GDSII generation, working closely with cross-functional teams across the globe.
What You’ll Be Doing:
- Lead full-chip physical implementation for complex SoC and ASIC designs.
- Define and drive chip-level physical design strategies, methodologies and best practices.
- Coordinate closely with RTL, STA, DFT, Packaging, Foundry and EDA partners to achieve successful design closure.
- Mentor and coach Physical Design engineers, supporting capability development across the team.
- Review and approve block-level physical design deliverables before integration.
- Lead technical reviews, debug sessions and closure activities.
- Support recruitment activities and contribute to building a world-class Physical Design team.
- Represent Aion Silicon at universities, conferences and industry events, sharing technical expertise and promoting innovation.
- Ensure the team remains at the forefront of industry methodologies, tools and advanced-node technologies.
What We’re Looking For:
- 10+ years of Physical Design experience with a proven track record of full-chip delivery.
- Strong expertise in advanced technology nodes, including 7nm, 5nm and below.
- Experience delivering multiple complex SoC or ASIC tape-outs.
- Demonstrated leadership experience mentoring and developing engineers.
- Strong customer engagement and stakeholder management skills.
- Excellent communication skills with the ability to influence technical direction across multiple teams.
Technical Expertise:
- Full-Chip Floorplanning & Integration
- Chip-level floorplanning and macro placement
- IO ring integration
- Hierarchical and flat implementation flows
- Pin placement, channel planning and congestion management
- Power Planning & Package Integration
- Power grid design and optimisation
- Multi-voltage domains and power gating
- IR drop and electromigration analysis
- Bump planning and package co-design
- Clock Tree Synthesis
- Multi-domain and multi-level CTS
- Clock mesh, H-tree and fishbone architectures
- Skew, latency and jitter optimisation
- Low-power clocking techniques
- Placement, Routing & Timing Closure
- Full-chip placement and routing
- Signal integrity, crosstalk and antenna resolution
- MCMM timing analysis
- STA sign-off and timing ECO implementation
- Hierarchical timing budgeting and closure
- Physical Verification & Tape-Out
- DRC, LVS and ERC sign-off
- RC extraction and correlation
- Reliability and noise analysis
- GDSII/OASIS generation and foundry handoff
EDA Tool Expertise:
- Strong working knowledge of one or more industry-leading tool flows, including:
- Synopsys (ICC2, Fusion Compiler, PrimeTime, StarRC, ICV)
- Cadence (Innovus, Tempus, Voltus, Genus)
- Mentor Calibre
Desirable Experience:
- DFT integration and ECO flows
- 2.5D/3D-IC and chiplet-based architectures
- Advanced packaging technologies
- Master's or PhD in a relevant engineering discipline
Personal Attributes:
- Leads through collaboration, trust and transparency.
- Thrives in a fast-paced environment and enjoys solving complex technical challenges.
- Demonstrates strong ownership and accountability.
- Has a passion for mentoring and developing others.
- Is adaptable, resilient and able to navigate changing priorities.
- Embodies Aion Silicon's values and contributes positively to our culture.
Why Join Aion Silicon?
At Aion Silicon, you will work alongside exceptional engineers on some of the industry's most challenging semiconductor projects. You will have the opportunity to influence technical strategy, mentor future talent, and help shape the next generation of silicon solutions. If you are a recognised Full-Chip Physical Design expert ready to make a significant impact, we would love to hear from you. Apply today and help us design the future.
Principal Physical Design Engineer (Full Chip Expert) in London employer: Aion Silicon
As a leading semiconductor company in the UK, we pride ourselves on fostering a culture of innovation and technical excellence. Our employees benefit from a collaborative work environment that encourages professional growth through continuous learning and development opportunities. With a focus on cutting-edge technology and a commitment to employee well-being, we offer a rewarding career path for those looking to make a significant impact in the industry.
