At a Glance
- Tasks: Join AMD's CPU Cores team as a DFT engineer, working on next-gen CPU designs.
- Company: AMD is a leader in technology, transforming lives with innovative computing solutions.
- Benefits: Enjoy flexible work options, competitive pay, and a collaborative culture.
- Why this job: Be part of a cutting-edge team tackling the world's biggest tech challenges.
- Qualifications: Strong background in DFT methodologies and excellent communication skills required.
- Other info: Opportunities for mentorship and growth in a diverse, inclusive environment.
The predicted salary is between 48000 - 72000 £ per year.
WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SR. STAFF DFT ENGINEER( TECH LEAD) T HE ROLE : We are seeking a highly experienced DFT engineer to join our CPU Cores team in Cambridge, UK. The ideal candidate will have a strong technical background and extensive experience in DFT methodologies, particularly in the context of CPU core design and development. As a DFT engineer in AMD\’s CPU Cores team, you will have an outstanding opportunity to work on AMD’s next-generation CPU core designs. You will work as part of an experienced, skilled, and motivated engineering team with a track record of success. You will help make AMD’s ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology. As a senior member within the DFT team, you will work closely with the Architecture, Design, Verification, Physical Design teams and Product Engineers to achieve first pass silicon success. THE PERSON: A successful candidate will exhibit exceptional knowledge in Design for Testability (DFT) and possess extensive experience, complemented by a robust, self-motivated work ethic and strong leadership qualities. The ideal candidate should demonstrate a genuine passion for modern, complex processor architectures, digital design and verification, and an overall enthusiasm for DFT. As a collaborative team player, you will have outstanding communication skills and experience in working effectively with engineers across various locations and time zones. Your strong analytical and problem-solving abilities will empower you to tackle challenges enthusiastically and with a willingness to learn. Additionally, you should have a keen eye for detail and the capability to think critically. The role requires a proactive self-starter who can take initiative and independently drive tasks to successful completion. K EY RESPONSIBLITIES : Strong prior experience in all or at least some of the key areas below would be needed Keep abreast with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies in to AMD products. Define and implement DFT architecture and features for next generation multi-core microprocessor designs and support their verification effort. Work closely with architects, design, verification, physical design and product engineering teams to integrate DFT requirements seamlessly into the overall design process and to develop scalable DFT architectures for complex CPU designs. Coordinate with DFT teams across different time zones to develop unified DFT strategies, promoting effective communication and collaboration. Work closely with DFT Tool Vendors and drive improvements based on the testability requirements. Develop efficient DFx flows and methodology compatible with front end and back end design flows. Work with the product, test engineering teams and post-silicon debug teams to ensure successful silicon bring up, to help root-cause any silicon failures and to enhance yield learning & improvement. Mentor and coach junior engineers P REFERRED EXPERIENCE : Strong prior experience in all or at least some of the key areas below would be preferred Prior work experience in hi gh-performance and low-power designs would be a huge bonus. Understanding of low-power design flows such as power/clock gating, multi-Vt and voltage/frequency scaling etc will be a plus. Good understanding of DFT components like JTAG(IEEE 1149.x), IJTAG(IEEE P1687), Core Test(IEEE P1500), SSN(Streaming Scan Network), SSH, Test Compression, OCC etc. Excellent Verilog RTL coding, scripting( using Python, Perl, Shell, TCL, Awk, Sed etc) and debugging skills are critical Strong experience in Scan based testing and industry standard ATPG CAD tools desired. Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, Cell Aware etc. Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other state of the art EDA tools. Experience in MBIST implementation and verification will be a strong plus. Good understanding of STA concepts having handled DFT timing closure before would be a plus. Experience in Spyglass based DFT DRC checks at RTL level would be a plus. Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler etc would be a plus. Prior experience in working with Version control systems like perforce, git etc would be critical. Understanding of Logic Equivalence, CDC, Lint, UPF/CLP checks would be a plus. Familiarity with System Verilog and UVM would be a plus. Exposure to post-silicon testing and tester pattern debug are major assets. Strong problem solving and debug skills across various levels of design hierarchies. Must have good communication skills and the ability to work in a worldwide team environment. ACADEMIC CREDENTIALS: Bachelors or Masters or PhD in Computer engineering/Electrical engineering/Electronics Engineering #LI-PL1 #LI-Hybrid #CORE Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr
SR. STAFF DFT ENGINEER(TECH LEAD) employer: Advanced Micro Devices
Contact Detail:
Advanced Micro Devices Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land SR. STAFF DFT ENGINEER(TECH LEAD)
✨Tip Number 1
Familiarise yourself with AMD's latest CPU technologies and DFT methodologies. Understanding their current projects and innovations will not only help you in interviews but also show your genuine interest in the role.
✨Tip Number 2
Network with current or former AMD employees on platforms like LinkedIn. Engaging with them can provide insights into the company culture and expectations, which can be invaluable during your application process.
✨Tip Number 3
Prepare to discuss specific DFT challenges you've faced in previous roles. Be ready to share examples of how you collaborated with cross-functional teams, as teamwork is a key aspect of the position.
✨Tip Number 4
Stay updated on industry trends related to DFT and CPU design. Being knowledgeable about the latest advancements will demonstrate your commitment to continuous learning and innovation, aligning with AMD's mission.
We think you need these skills to ace SR. STAFF DFT ENGINEER(TECH LEAD)
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience in Design for Testability (DFT) and any relevant projects you've worked on. Use specific examples that demonstrate your technical skills and leadership qualities, particularly in CPU core design.
Craft a Compelling Cover Letter: In your cover letter, express your passion for modern processor architectures and your enthusiasm for DFT. Mention how your background aligns with AMD's mission and culture, and provide examples of how you've successfully collaborated with cross-functional teams.
Showcase Relevant Skills: Clearly outline your technical skills related to DFT methodologies, such as your experience with JTAG, Verilog RTL coding, and scripting languages. Highlight any familiarity with industry-standard tools and techniques that are mentioned in the job description.
Proofread and Edit: Before submitting your application, thoroughly proofread your documents for any spelling or grammatical errors. Ensure that your application is clear, concise, and free of jargon, making it easy for the hiring team to understand your qualifications.
How to prepare for a job interview at Advanced Micro Devices
✨Showcase Your DFT Expertise
Make sure to highlight your extensive experience in Design for Testability (DFT) methodologies. Be prepared to discuss specific projects where you successfully implemented DFT techniques, particularly in CPU core design.
✨Demonstrate Collaboration Skills
Since the role involves working closely with various teams, emphasise your ability to collaborate effectively across different time zones. Share examples of how you've successfully coordinated with diverse teams in past projects.
✨Stay Updated on Industry Trends
Research the latest trends and advancements in the DFT domain before your interview. Being knowledgeable about current technologies will show your passion for the field and your commitment to continuous learning.
✨Prepare for Technical Questions
Expect technical questions related to DFT components and methodologies. Brush up on your knowledge of JTAG, ATPG tools, and fault models, as well as your coding skills in Verilog and scripting languages like Python or TCL.