Design For Test - DV Engineer

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We are seeking an experienced DFT Design Verification (DFT DV) engineer to join our CPU Cores team in Cambridge, UK. The ideal candidate will have a strong technical background and experience in DFT and DV methodologies, particularly in the context of CPU core design and development. As a DFT DV engineer in AMD's CPU Cores team, you will have an outstanding opportunity to work on AMD’s next-generation CPU core designs. You will work as part of an experienced, skilled and motivated engineering team with a strong track record for success. You will help make AMD’s ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology.

As a senior member within the DFT team, you will work closely with the Architecture, Design, Verification, Physical Design teams and Product Engineers to achieve first pass silicon success. This role involves performing DFT verification tasks for AMD's next generation CPU Cores which are high-performance, energy efficient designs targeted for client, desktop and data center CPU markets.

The ideal candidate should demonstrate a genuine passion for modern, complex processor architectures, design and verification and an overall enthusiasm for DFT. As a collaborative team player, you will have outstanding communication skills and experience in working effectively with engineers across various locations and time zones. Your strong analytical and problem-solving abilities will empower you to tackle challenges enthusiastically and with a willingness to learn. A successful candidate will exhibit strong design verification knowledge and experience, complemented by a robust, self-motivated work ethic and strong leadership qualities. Additionally, you should have a keen eye for detail and the capability to think critically. The role requires a proactive self-starter who can take initiative and independently drive tasks to successful completion.

KEY RESPONSIBILITIES

• Verify advanced Design for Test (DFT) functions such as Scan, Memory BIST, JTAG/IJTAG/P1500 and partitioned test structures.
• Work with architects, designers and post silicon teams to come up with detailed test plan to verify the new features.
• Develop test benches and build directed and random verification tests to verify DFT implementation at RTL/gate-level and provide timely feedback to the designers.
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
• Work on code/functional coverage improvements to achieve design verification metrics defined for various project milestones.
• Co-ordinate with test engineers and generate high quality test patterns and DV tests to run on Silicon.
• Act as a bridge between test engineers and design teams in debugging silicon failures and provide support to triage the issue till it is resolved.
• Collaborate with other DFT DV team members across various sites and time zones to innovate and improve DV methodologies/flows, develop unified DFT DV strategies and to share best practices.
• Mentor and coach junior engineers.

PREFERRED EXPERIENCE

• Solid DFT verification skills using Verilog, System Verilog, C/C++/Assembly, OOP, Perl/Python etc.
• Good understanding of Design for Test architecture and methodologies (e.g. JTAG(IEEE 1149.x), IJTAG(IEEE P1687), Core Test(IEEE P1500), Scan, MBIST etc.)
• Strong skills in Verilog simulation and debugging using simulation tools (like VCS), Verilog RTL etc.
• Prior experience in working with version control systems like perforce, git etc would be critical.
• Write, maintain and enhance scripts using Perl, Python or other scripting languages.
• Prior exposure and strong desire to adopt AI capabilities in day-to-day DV workflow.
• Prior experience in UVM, Formal Verification, Assertion Based Verification flows etc would be given weightage.
• Experience in developing UVM based verification frameworks and testbenches, processes and flows and automating workflows in a distributed compute environment.
• Prior experience in working on high-performance, power efficient designs would be a bonus.
• Knowledge of advanced DFT components SSN(Streaming Scan Network), SSH, Test Compression, OCC etc.
• Knowledge of MBIST implementation flows and experience in MBIST DV will be a strong plus.
• Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other state of the art EDA tools.
• Exposure to post-silicon testing and tester pattern debug are major assets.
• Strong problem solving and debug skills across various levels of design hierarchies.
• Must have good communication skills and the ability to work in a worldwide team environment.
• Exposure to leadership or mentorship is an asset.

ACADEMIC CREDENTIALS

Bachelors or Masters degree in Computer/Electrical/Electronics Engineering.