Staff Design Verification Engineer in Cambridge

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centres, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s microprocessor IP, resulting in no bugs in the final design.

THE PERSON

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem‑solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
• Estimate the time required to write the new feature tests and any required changes to the test environment.
• Build the directed and random verification tests.
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.
• Develop an automated regression infrastructure setup for functional verification of high‑speed microprocessor designs.
• Develop interface assertions and work closely with the formal verification team.

PREFERRED EXPERIENCE

• Proficient in IP level ASIC verification.
• Working experience of memory subsystems would be a plus.
• Proficient in debugging firmware and RTL code using simulation tools.
• Proficient in using C++ testbenches and working in Linux and Windows environment.
• Experienced with Verilog, System Verilog, C, and C++ CPU pipeline knowledge.
• Automating workflows in a distributed compute environment.
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process.
• Strong background in the C++ language, preferably on Linux with exposure to Windows platform.
• Good understanding and hands‑on experience with SystemVerilog language.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset.
• Desirable assets with prior exposure to memory subsystem or other CPU unit verification.
• 3+ years of experience in Design Verification.

ACADEMIC CREDENTIALS

Bachelors or Masters degree in computer engineering/Electrical Engineering.