Key Responsibilities
- Help to inform technical decision-making and planning within the wider company, working with colleagues from Algorithm, System Architecture and Software teams.
- Take responsibility for the successful and timely delivery of projects by providing technical leadership
- Provide team leadership to build knowledge and support the development of individuals
- Work closely with other senior members of the hardware team to help translate product requirements into hardware team deliverables.
- Support discussions with customers during presales and product development
- Oversee the implementation of designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches
- Help to shape AccelerComm’s engineering methodology, processes, and design techniques, integrating AI where valuable.
- Nurture professional growth of team members through regular mentoring, coaching, and feedback
Skills, Knowledge & Expertise
- Track record of building and leading high performing collaborative teams
- Expert knowledge of RTL design (Verilog, SystemVerilog) for complex ASIC and FPGA products
- A strong skillset in delivery of digital designs for ASIC and FPGA
- Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis
- Expert user of EDA tools for simulation and synthesis
- Knowledge and appreciation of project management methodologies across the design lifecycle including agile and waterfall, requirements capture and traceability.
- Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming)
- Understanding of UVM verification techniques or practical experience using UVM for IP verification
- Experience with high speed interfaces on and off chip such as AMBA, PCI-E or JESD
- Understanding of using C++/SystemC for design modelling and integration
- Experience in Technology Readiness Models
- Understanding of system architecture of a multi-disciplinary team project
Job Benefits
We offer a bonus scheme which pays up to 20% of salary annually, depending on performance. This is in addition to EMI share options, issued periodically. We offer a range of good quality company benefits including pension and private health insurance.
We operate flexible working hours and offer hybrid working.
Design Team Leader in Cambridge employer: AccelerComm
As a Defence Systems Engineer at our innovative company, you will be part of a dynamic team dedicated to advancing cutting-edge EO/IR technologies. We pride ourselves on fostering a collaborative work culture that encourages professional growth and development, offering numerous opportunities for skill enhancement and career progression. Located in a vibrant area, our workplace not only provides a stimulating environment but also unique advantages such as access to industry-leading resources and a commitment to employee well-being.
