2 x FPGA Design Engineer: High-speed Digital Logic Design

2 x FPGA Design Engineer: High-speed Digital Logic Design

Join to apply for the 2 x FPGA Design Engineer: High-speed Digital Logic Design role at HyperCIM Ltd

2 x FPGA Design Engineer: High-speed Digital Logic Design

Join to apply for the 2 x FPGA Design Engineer: High-speed Digital Logic Design role at HyperCIM Ltd

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FPGA Design Engineer: High-speed Digital Logic Design

Location: Hybrid (Cambridge / Bristol with remote flexibility)

Reports to: CTO

Job Type: Full-Time, 6-Month Contract (potential to convert to permanent)

Compensation: Competitive salary + significant early-stage equity (for permanent role)

About Us

HyperCIM is redefining data intelligence with next-generation AI database accelerators that offload and optimise online database operations, transforming them into AI-ready workloads within the same pipeline. Our hardware-accelerated architecture enables real-time transactional AI at scale, eliminating bottlenecks in data-intensive environments.

We empower industries such as finance, telecom, e-commerce, and cloud infrastructure to achieve ultra-low latency and high-throughput decision-making, turning raw data into immediate, actionable insights.

Central to our platform is the Lambda Processing Unit (LPU), an innovative advancement in high-performance, energy-efficient computing. The LPU redefines the interaction between databases and artificial intelligence, setting a new benchmark for speed, efficiency, and scalability in data processing.

About the Roles

To further test and develop our LPU architecture in dominant use cases, we are now seeking an experienced high-speed digital logic design engineers to help advance us toward production readiness.This is a hands-on, technically challenging role in a fast-moving environment, where your contributions will directly shape the performance and scalability of our hardware.

You will work closely with the CTO and engineering leadership to design, implement, and optimise high-speed digital logic across FPGA and ASIC targets. The work spanspipelined datapaths, memory interfaces, concurrent logic, and architectural evaluation.

This isnot a project management or oversight role. It is adirect engineering rolefor those who enjoy working close to the silicon and solving deep technical problems from first principles.

Key Responsibilities

• Design, develop, and verify FPGA modules in Verilog/SystemVerilog and VHDL
• Translate novel functional computing models intooptimisedRTL architectures
• Implementhigh-throughput, pipelined digital logic and memory interfaces
• Contribute to simulation, synthesis,debug, and validation of designs onAlteraAgilexFPGAsand/orAMD Xilinx Versal
• Collaborate on architectural evaluation of latency, power, and scalability
• Write clean, maintainable RTL and contribute to documentation, DFT/DFM, and version control workflows

Qualifications

Education

BSc (2.1 or better) and/or MSc or higher in Electronic Engineering or related field. Academic grounding in Embedded CPUs and CPU Programming (Assembler and High-Level Languages)

Industry Experience

• Minimum 7 years of post-graduate experience in digital hardware design (FPGA/ASIC) and Verilog/SystemVerilog experience (or 15 years total experience with strong VHDL background)
• At least 2 years working with high-level logic synthesis and simulation tools
• 3 years hands-on experience with Intel Quartus Prime Pro toolchain
• PCIe Gen 3+ designs incorporating DDR4/5 memory or PCIe interfaces (or equivalent).
• 1-year minimum experience programming embedded RISC CPUs in C/C++

Technical Skills

• Designing for 3GHz+ operating speeds and wide buses (256 bits and wider).
• Familiarity with floating point logic, wide multiplexers, multiply-accumulators, look-up tables, and comparators.
• RTL design in Verilog/SystemVerilog and/or VHDL
• Simulation, timing closure, resource/power optimization
• Pipelined datapath and finite state machine specification and implementation.
• Familiarity with design-for-manufacture (DFM) and design-for-test (DFT) principles
• Experience with Xilinx or Altera FPGA-SOC toolchains.
• Comfortable working in both Linux and Windows environments

Nice to haves

• PCI3 Gen 6 experience
• Experience with Intel/Altera Agilex 5E FPGAs
• VHDL
• Exposure to compute-in-memory, functional or dataflow architectures
• UVM or equivalent verification experience
• Passion for documentation, mentorship, and systems-level thinking

Toolchain & Languages

• Git, Jira

What We Offer

• Competitive compensation and significant early-stage equity
• A supportive and flexible work culture.
• High ownership in a deeply technical startup environment
• Collaborate with world-class engineers and visionary leadership
• A principled engineering culture: clarity, trust, precision

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  Semiconductor Manufacturing

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