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- Tasks: Develop and maintain testbenches, lead verification components, and debug test failures.
- Company: Join a globally recognised semiconductor company innovating with RISC-V architecture.
- Benefits: Enjoy a dynamic work environment with opportunities for growth and development.
- Why this job: Be part of a strategic shift in technology and contribute to exciting new products.
- Qualifications: 5+ years in IP-level verification with expertise in SystemVerilog UVM required.
- Other info: Collaborate closely with designers and improve verification efficiency.
The predicted salary is between 48000 - 72000 £ per year.
My client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap.
They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join.
Principal Verification Engineer
Responsibilities:
- Develop and maintain SystemVerilog UVM testbenches for complex IPs.
- Lead the creation of new UVM verification components and contribute to testbench architecture
- Debug test failures and define functional coverage models to ensure sign-off quality.
- Work closely with designers and contribute to verification strategy during design and concept phases.
- Improve verification efficiency and ensure compliance with functional safety and quality standards.
Requirements:
- Minimum 5 years of IP-level verification experience using SystemVerilog UVM.
- Strong understanding of UVM methodology, SVAs, and verification metrics.
- Ability to interpret complex design specifications and create robust verification environments.
- Proficiency in industry-standard EDA tools and scripting languages.
- Excellent communication skills and a methodical, detail-focused approach.
Apply to learn more!
Principal Verification Engineer employer: Platform Recruitment
Contact Detail:
Platform Recruitment Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Principal Verification Engineer
✨Tip Number 1
Familiarise yourself with the latest advancements in RISC-V architecture. Understanding the nuances of this technology will not only help you during interviews but also demonstrate your genuine interest in the company's direction.
✨Tip Number 2
Network with current employees or industry professionals who have experience in verification engineering. Engaging in conversations about their experiences can provide valuable insights and potentially lead to referrals.
✨Tip Number 3
Brush up on your SystemVerilog UVM skills by working on personal projects or contributing to open-source initiatives. This hands-on experience will enhance your practical knowledge and make you a more attractive candidate.
✨Tip Number 4
Prepare to discuss specific examples of how you've improved verification efficiency in past roles. Being able to articulate your contributions to functional safety and quality standards will set you apart from other candidates.
We think you need these skills to ace Principal Verification Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience with SystemVerilog UVM and any relevant projects you've worked on. Emphasise your understanding of UVM methodology and your ability to create robust verification environments.
Craft a Compelling Cover Letter: In your cover letter, explain why you're excited about the opportunity to work with a globally recognised semiconductor company. Mention your experience in IP-level verification and how it aligns with their needs for functional verification across complex IPs.
Showcase Relevant Projects: Include specific examples of past projects where you developed or maintained testbenches, debugged test failures, or improved verification efficiency. This will demonstrate your hands-on experience and problem-solving skills.
Highlight Communication Skills: Since the role requires collaboration with designers and contributing to verification strategy, make sure to mention any experiences that showcase your excellent communication skills and your methodical approach to detail.
How to prepare for a job interview at Platform Recruitment
✨Showcase Your Technical Expertise
Be prepared to discuss your experience with SystemVerilog and UVM in detail. Highlight specific projects where you've developed testbenches or debugged complex IPs, as this will demonstrate your hands-on knowledge and problem-solving skills.
✨Understand the Company’s Technology Roadmap
Research the company's recent developments, especially their shift towards RISC-V architecture. This will not only show your interest but also allow you to align your answers with their strategic goals during the interview.
✨Prepare for Scenario-Based Questions
Expect questions that assess your ability to handle real-world verification challenges. Think of examples where you improved verification efficiency or dealt with functional safety standards, and be ready to explain your thought process.
✨Communicate Clearly and Effectively
Since excellent communication skills are a requirement, practice explaining complex technical concepts in simple terms. This will help you connect with the interviewers and demonstrate your ability to work collaboratively with designers.
