Find a job 
Featured Companies 
Featured Universities 
For Companies At a Glance
- Tasks: Lead the layout of complex RFICs and collaborate with design teams.
- Company: Join Qualcomm, a leader in wireless technology and innovation.
- Benefits: Enjoy a dynamic work environment with opportunities for mentorship and growth.
- Why this job: Be part of cutting-edge IoT developments and make a real impact in technology.
- Qualifications: Bachelor's degree or higher in Engineering with relevant experience in RFIC design.
- Other info: Open to candidates with equivalent experience; diverse and inclusive workplace.
The predicted salary is between 43200 - 72000 £ per year.
Qualcomm Farnborough, England, United Kingdom
Join or sign in to find your next job
Join to apply for the Staff RFIC Physical Design Engineer role at Qualcomm
Qualcomm Farnborough, England, United Kingdom
Join to apply for the Staff RFIC Physical Design Engineer role at Qualcomm
Company
Qualcomm Technologies International Ltd
Job Area
Engineering Group, Engineering Group > ASICS Engineering
General Summary
We are searching for a Staff level radio frequency integrated circuit (RFIC)/Analogue layout engineer to join a strong group of RFIC designers to help lead Qualcomm in the development of RF transceivers to address the IoT market. Working within a dynamic design team you will participate in the development of next generation RFIC products in the IoT wireless space.
Responsibilities
- Lead the physical layout of complex RFICs.
- Define and enforce layout methodologies, best practices, and quality standards across the layout team.
- Collaborate with RFIC design, packaging, and verification teams to ensure optimal performance and manufacturability.
- Drive technical reviews, mentor junior and senior layout engineers, and provide layout planning support to project lead.
- Own the full layout lifecycle from floorplanning to tape-out, including DRC/LVS/PEX sign-off and post-layout optimization.
Profile
- Highly motivated, pro-active self-starter
- Strong sense of ownership and responsibility
- Creative thinker with strong problem-solving skills
- Team oriented attitude
- Ability to thrive in a multicultural environment
- Ability to communicate well with cross-functional teams
- Excellent written and oral communications skills
Minimum Qualifications
- Bachelor\’s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master\’s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Required Experience
- 10+ years of hands-on RFIC layout experience in advanced CMOS and/or BiCMOS technologies.
- Full appreciation of RF and analogue layout techniques in low geometry nodes (22nm or lower)
Required Detailed Knowledge
- Expert-level proficiency in Cadence Virtuoso and advanced layout techniques for RF blocks (LNAs, mixers, VCOs, PAs, PLLs).
- Deep understanding of parasitic-aware layout, matching, shielding, isolation, and substrate noise mitigation.
- Strong command of DRC, LVS, and PEX flows, including debugging and optimization.
- Familiarity with ESD, latch-up prevention, and reliability-aware layout practices.
- Experience with layout planning for high-density, high-performance RFICs.
Preferred Detailed Knowledge
- Scripting and automation using SKILL, Python, or TCL to enhance layout productivity.
- Familiarity with advanced process nodes (e.g., 16nm, 7nm) and 3DIC/heterogeneous integration.
- Knowledge of EM simulation tools (e.g., HFSS, Momentum) and their integration into layout flows.
Additional Useful Experience
- Exposure to RFIC design principles and ability to interpret schematics and simulation results.
- Contributions to EDA tool evaluation, layout methodology development, or academic publications.
- Cross-site collaboration and experience working in global teams.
Key Words
- CMOS
- IoT
- RF and analogue layout
- Cadence
- +10 years’ experience in RFIC design
- References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm\’s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
If you would like more information about this role, please contact Qualcomm Careers.
3076058
Seniority level
-
Seniority level
Not Applicable
Employment type
-
Employment type
Full-time
Job function
-
Job function
Other
-
Industries
Telecommunications
Referrals increase your chances of interviewing at Qualcomm by 2x
Cabin Interiors – Design & Certification Engineer
Frimley, England, United Kingdom 1 week ago
Senior Physical Design Engineer – UK Reading – Cisco Silicon One
Reading, England, United Kingdom 3 days ago
West Byfleet, England, United Kingdom 2 weeks ago
Cabin Interiors – Design and Certification Engineer
Frimley, England, United Kingdom 1 week ago
Frimley, England, United Kingdom 1 day ago
Reading, England, United Kingdom 1 month ago
Guildford, England, United Kingdom 4 months ago
Struct & Payload Design Engr (Struct & Payload Design Engr-General)
Frimley, England, United Kingdom 6 days ago
Reading, England, United Kingdom 1 week ago
Pangbourne, England, United Kingdom 2 weeks ago
Reading, England, United Kingdom 1 month ago
Reading, England, United Kingdom 1 month ago
Reading, England, United Kingdom 1 week ago
Reading, England, United Kingdom 3 days ago
Farnborough, England, United Kingdom 2 weeks ago
West Byfleet, England, United Kingdom 1 week ago
Sunbury-On-Thames, England, United Kingdom 4 days ago
Reading, England, United Kingdom 6 days ago
London, England, United Kingdom 1 year ago
Reading, England, United Kingdom 6 days ago
We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr
Staff RFIC Physical Design Engineer employer: Qualcomm
Contact Detail:
Qualcomm Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Staff RFIC Physical Design Engineer
✨Tip Number 1
Make sure to showcase your leadership experience in RFIC layout during networking events or informal meetups. Engaging with professionals in the field can help you gain insights and potentially get referrals.
✨Tip Number 2
Familiarise yourself with the latest advancements in RFIC technologies, especially in IoT applications. Being knowledgeable about current trends will allow you to have informed discussions during interviews.
✨Tip Number 3
Connect with current or former Qualcomm employees on platforms like LinkedIn. They can provide valuable information about the company culture and the specifics of the role, which can help you tailor your approach.
✨Tip Number 4
Prepare to discuss your experience with Cadence Virtuoso and advanced layout techniques in detail. Be ready to share specific examples of how you've applied these skills in past projects, as this will demonstrate your expertise.
We think you need these skills to ace Staff RFIC Physical Design Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your relevant experience in RFIC layout and ASIC design. Emphasise your hands-on experience with advanced CMOS and BiCMOS technologies, as well as any leadership roles you've held.
Craft a Strong Cover Letter: In your cover letter, express your enthusiasm for the role at Qualcomm and how your skills align with their needs. Mention specific projects or achievements that demonstrate your expertise in RFIC design and layout methodologies.
Showcase Technical Skills: Clearly outline your proficiency in tools like Cadence Virtuoso and any scripting languages you know, such as Python or TCL. Highlight your understanding of DRC, LVS, and PEX flows, as these are crucial for the role.
Prepare for Technical Questions: Anticipate technical questions related to RFIC design and layout during the interview process. Be ready to discuss your problem-solving approach and how you've successfully led layout teams in previous roles.
How to prepare for a job interview at Qualcomm
✨Showcase Your Technical Expertise
Make sure to highlight your extensive experience with RFIC layout, especially in advanced CMOS and BiCMOS technologies. Be prepared to discuss specific projects where you led successful tape-outs and how you applied your knowledge of DRC, LVS, and PEX flows.
✨Demonstrate Leadership Skills
Since the role involves mentoring junior engineers and leading layout teams, share examples of how you've successfully guided others in previous positions. Discuss your approach to fostering collaboration and ensuring quality standards within a team.
✨Prepare for Technical Questions
Expect in-depth questions about layout methodologies, parasitic-aware design, and isolation techniques. Brush up on your understanding of ESD and latch-up prevention, as well as any relevant scripting or automation tools you’ve used to enhance productivity.
✨Communicate Effectively
Strong communication skills are essential for this role. Practice articulating complex technical concepts clearly and concisely, as you'll need to collaborate with cross-functional teams. Be ready to explain your thought process during technical reviews and how you handle feedback.
