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- Tasks: Write test plans, develop software tests, and debug issues in a dynamic team environment.
- Company: Join a forward-thinking tech company focused on innovative hardware solutions.
- Benefits: Enjoy hybrid working, competitive pay, and a supportive work culture.
- Why this job: Be part of exciting projects that shape the future of technology while working flexibly.
- Qualifications: Experience in Verilog/System Verilog and SoC verification is essential; 6-20 years preferred.
- Other info: This is a 6-month contract with opportunities for growth and learning.
The predicted salary is between 36000 - 60000 £ per year.
As a Verification Engineer, you will be writing test plans, defining test methodologies, developing C based software tests, System Verilog/Verilog testbenches and tests, and debugging test failures and issues. You will also be working with project management and leads on planning tasks, schedules, and reporting process.
The must haves:
- Proven understanding of digital hardware verification language Verilog/System Verilog HDL.
- Experience in SoC verification using embedded low-level programming including C/C++ Tests and assembly language.
- Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, test bench implementation, test case development, documentation, and support.
- Knowledge of SoC Verification Flow and strategy.
- 6-20 years of experience of SoC verification.
This is a 6-month contract. A day rate, in-scope IR35. Competitive pay rate. This role provides hybrid working access from the comforts of your own home and only going to our state-of-the-art office in Bristol - 2 days a week.
Once you’ve applied, one of our friendly recruitment consultants will give you a call and talk you through the screening process. If your application is successful, you’ll be involved in a live virtual interview with one of our client’s hiring managers to get to know you better.
We look forward to speaking to you!
Software Verification Engineer employer: Hays
Contact Detail:
Hays Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Software Verification Engineer
✨Tip Number 1
Familiarise yourself with the latest trends and tools in digital hardware verification, especially Verilog and System Verilog. This knowledge will not only help you during the interview but also demonstrate your commitment to staying updated in the field.
✨Tip Number 2
Prepare to discuss specific projects where you've implemented SoC verification methodologies. Be ready to explain your role in the requirements collection, test plan creation, and any challenges you faced, as this will showcase your hands-on experience.
✨Tip Number 3
Practice articulating your debugging process for test failures. Being able to clearly explain how you approach problem-solving will highlight your analytical skills and technical expertise, which are crucial for a Verification Engineer.
✨Tip Number 4
Engage with our recruitment team before your interview. They can provide insights into what the hiring managers are specifically looking for, allowing you to tailor your responses and demonstrate that you're the perfect fit for the role.
We think you need these skills to ace Software Verification Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience with digital hardware verification languages like Verilog/System Verilog HDL. Include specific examples of your work in SoC verification and any relevant projects you've completed.
Craft a Strong Cover Letter: In your cover letter, express your enthusiasm for the role and the company. Mention your understanding of the verification process and how your skills align with the job requirements, particularly in writing test plans and methodologies.
Showcase Relevant Experience: When detailing your experience, focus on your exposure to all stages of verification. Highlight your ability to create verification methodology plans, develop test cases, and document processes effectively.
Prepare for the Interview: Research common interview questions for Software Verification Engineers. Be ready to discuss your previous projects, particularly those involving C/C++ tests and assembly language, and how you approach debugging test failures.
How to prepare for a job interview at Hays
✨Showcase Your Technical Skills
Be prepared to discuss your experience with Verilog/System Verilog HDL and C/C++ programming. Bring examples of past projects where you developed test plans or debugged issues, as this will demonstrate your hands-on expertise.
✨Understand the Verification Flow
Familiarise yourself with the SoC verification flow and strategy. Be ready to explain how you've contributed to each stage, from requirements collection to documentation, as this shows your comprehensive understanding of the process.
✨Communicate Effectively
Since you'll be working closely with project management and leads, practice articulating your thoughts clearly. Prepare to discuss how you plan tasks and report progress, as effective communication is key in collaborative environments.
✨Ask Insightful Questions
Prepare thoughtful questions about the company's verification methodologies and team dynamics. This not only shows your interest in the role but also helps you gauge if the company culture aligns with your values.
