Physical Design Engineer - Foundry Team

Position Summary

Samsung Semiconductor is a leading provider of industry-leading semiconductor solutions, enabling innovative growth in segments such as System LSI, Memory, and Foundry. Our engineers work on cutting-edge technologies including Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/6G, Neural processors, Serial Interfaces, Multimedia IPs, and more. As one of the largest R&D centers outside Korea, we pride ourselves on working on advanced technologies. Our engineers collaborate across diverse domains, projects, and countries, conducting research in emerging technology areas. Innovation and creativity are highly valued as we aim to deliver high reliability, high performance, and value-added services to support Samsung Electronics' world-class products.

Roles and Responsibilities:

• Design and implement physical design and timing closure for complex SOCs, including mobile application processors, modem sub-systems, and connectivity chips, using synthesis, place and route, STA, and physical signoff tools.
• Perform top-level floor planning, including partition shaping, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning.
• Optimize for timing, power, and area trade-offs to achieve optimal PPA.
• Utilize industry-standard tools such as ICC, DC, PT, VSLP, Redhawk, Calibre, and Formality effectively.
• Develop and maintain scripts using Perl/Tcl to automate design flows.
• Work with large SOC designs (>20M gates) operating at frequencies above 1GHz.
• Perform block-level and full-chip SDC cleanup, synthesis optimization, low power checking, and logic equivalence checking.
• Address challenges related to deep sub-micron designs (8nm/5nm), including manufacturability, power, and signal integrity issues.
• Manage SOC issues such as multiple voltage and clock domains, ESD strategies, mixed-signal integration, and package interactions.
• Implement hierarchical and top-down design methodologies, including budgeting, timing, and physical convergence.
• Debug LVS/DRC issues at chip and block levels using physical design verification methods.
• Participate in recent successful SOC tape-outs.

Experience: 5+ years in physical design and implementation.

Qualifications: B.Tech/B.E or M.Tech/M.E degree.

Disclaimer: Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd, is committed to diversity and equal employment opportunity, regardless of religion, gender, age, marital status, gender identity, veteran status, genetic information, disability, or other protected characteristics.