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- Tasks: Write test plans, develop software tests, and debug issues in a dynamic team.
- Company: Join a forward-thinking company focused on innovative technology solutions.
- Benefits: Enjoy hybrid working, competitive pay, and a supportive work culture.
- Why this job: Be part of exciting projects that shape the future of technology while working flexibly.
- Qualifications: Experience in Verilog/System Verilog and SoC verification is essential.
- Other info: This is a 6-month contract with opportunities for growth and learning.
The predicted salary is between 42000 - 84000 £ per year.
As a Verification Engineer, you will be writing test plans, defining test methodologies, developing C based software tests, System Verilog/Verilog testbenches and tests, and debugging test failures and issues. You will also be working with project management and leads on planning tasks, schedules, and reporting process.
The must haves:
- Proven understanding of digital hardware verification language Verilog/System Verilog HDL.
- Experience in SoC verification using embedded low-level programming including C/C++ Tests and assembly language.
- Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, test bench implementation, test case development, documentation, and support.
- Knowledge of SoC Verification Flow and strategy.
- 6-20 years of experience of SoC verification.
This is a 6-month contract. A day rate, in-scope IR35. Competitive pay rate. This role provides hybrid working access from the comforts of your own home and only going to our state-of-the-art office in Bristol - 2 days a week.
Once you’ve applied, one of our friendly recruitment consultants will give you a call and talk you through the screening process. If your application is successful, you’ll be involved in a live virtual interview with one of our client’s hiring managers to get to know you better.
We look forward to speaking to you!
Software Verification Engineer employer: Hays
Contact Detail:
Hays Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Software Verification Engineer
✨Tip Number 1
Familiarise yourself with the latest trends and tools in digital hardware verification, especially Verilog and System Verilog. Being able to discuss recent advancements or challenges in these areas during your interview can really set you apart.
✨Tip Number 2
Prepare to demonstrate your problem-solving skills by thinking of specific examples where you've debugged test failures or issues in previous roles. This will show your practical experience and ability to handle real-world challenges.
✨Tip Number 3
Since this role involves collaboration with project management, brush up on your communication skills. Be ready to discuss how you've effectively worked with teams in the past to plan tasks and manage schedules.
✨Tip Number 4
Research the company culture and values of our client. Understanding their work environment and what they value in employees can help you tailor your responses during the interview to align with their expectations.
We think you need these skills to ace Software Verification Engineer
Some tips for your application 🫡
Understand the Role: Before applying, make sure you fully understand the responsibilities of a Software Verification Engineer. Familiarise yourself with the key skills required, such as knowledge of Verilog/System Verilog and experience in SoC verification.
Tailor Your CV: Customise your CV to highlight relevant experience in digital hardware verification and C/C++ programming. Emphasise your familiarity with test plans, methodologies, and any specific projects that showcase your expertise in SoC verification.
Craft a Strong Cover Letter: Write a compelling cover letter that explains why you are a great fit for the role. Mention your years of experience, specific skills related to the job description, and your enthusiasm for working in a hybrid environment.
Proofread Your Application: Before submitting, carefully proofread your application materials. Check for any spelling or grammatical errors, and ensure that all information is clear and concise. A polished application reflects your attention to detail.
How to prepare for a job interview at Hays
✨Showcase Your Technical Skills
Be prepared to discuss your experience with Verilog/System Verilog and C/C++ in detail. Bring examples of past projects where you developed test plans or debugged issues, as this will demonstrate your hands-on expertise.
✨Understand the Verification Flow
Familiarise yourself with the SoC verification flow and strategy. Be ready to explain how you've contributed to each stage, from requirements collection to documentation, as this shows your comprehensive understanding of the process.
✨Ask Insightful Questions
Prepare thoughtful questions about the company's verification methodologies and project management processes. This not only shows your interest in the role but also helps you gauge if the company aligns with your career goals.
✨Demonstrate Team Collaboration
Since you'll be working closely with project management and leads, share examples of how you've successfully collaborated in previous roles. Highlight your communication skills and ability to work within a team to achieve common goals.
