Social network you want to login/join with:FPGA Design and Verification Engineer – 297, Londoncol-narrow-leftClient:Location:London, United KingdomJob Category:Other-EU work permit required:Yescol-narrow-rightJob Reference:d1296bd28263Job Views:9Posted:22.06.2025Expiry Date:06.08.2025col-wideJob Description:Science Led, Enterprise Driven – Accelerating Quantum ComputingQuantinuum is the world’s largest integrated quantum company, pioneering powerful quantum computers and advanced software solutions. Quantinuum’s technology drives breakthroughs in materials discovery, cybersecurity, and next-gen quantum AI. With approximately 500 employees, including 370+ scientists and engineers, Quantinuum leads the quantum computing revolution across continents.We unite best-in-class software with high-fidelity hardware to accelerate quantum computing. With integrated full-stack technology, our world-class team is rapidly scaling quantum computing.Quantinuum recently secured $300M in funding, visit our news pages to learn more about this and other Quantinuum scientific breakthroughs and achievements: https://www.quantinuum.com/newsWe are looking for a FPGA Design and Verification Engineer to design, simulate, and verify FPGA functionality for the electronic control systems that drive our next-generation quantum computers at our Broomfield, CO location. For this role, we are seeking someone with expertise in System Verilog, though VHDL and Verilog is a plus. Projects may include interfacing DACs/ADCs and DDRx memory, digital filtering and signal processing, digital control loops, and data formatting, as well as interfacing with other FPGAs, microcontrollers, high-speed serial components, and other low-speed peripherals and sensors.Key Responsibilities:Develop a complex electronic control system capable of controlling digital, analog, and RF signalsPerform FPGA design, simulation, and verificationCollaborate with PCB designers, software, and other engineers to complete projects on-time with first-pass successProvide technical expertise that informs future product development and process improvements across the organizationWork in R&D and production environmentsYOU MUST HAVE:Bachelor’s Degree MinimumMinimum 6+ years of engineering experienceDue to Contractual requirements, must be a U.S. Person. defined as, U.S. citizen permanent resident or green card holder, workers granted asylum or refugee statusDue to national security requirements imposed by the U.S. Government, candidates for this position must not be a People\’s Republic of China national or Russian national unless the candidate is also a U.S. citizen.WE VALUE:Masters/PhD degree in Electrical Engineering or related field10+ years of experience in the specification, development, and validation of complex electronic productsDemonstrated technical excellence and leadership in FPGA design and verification, including Xilinx software and IP, as well as mastery of System Verilog, Verilog, and VHDLVerification and simulation experience with QuestaSim, QVIP, and related toolsEmbedded software experience, especially involving Zynq Ultrascale+ FPGAs and processorsProven leadership ability that includes program execution and skills development and mentoring of other engineers and techniciansAbility to consistently demonstrate decisive business impact and continuous drive for improvement in an ambiguous environmentStrong communication skills and “right size” design documentationEstimated Salary Wage: $129,000 – $174,000 AnnuallyWhat is in it for you?-A competitive salary and innovative, game-changing work-Employer subsidized health, dental, and vision insurance-401(k) match for student loan repayment benefit-Equity, 401k retirement savings plan + 12 Paid holidays and generous vacation + sick time-Paid parental leaveQuantinuum is an equal opportunity employer. You will be considered without regard to age, race, creed, color, national origin, ancestry, marital status, affectional or sexual orientation, gender identity or expression, disability, nationality, sex, or veteran status. #J-18808-Ljbffr
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