Design Engineer & Senior Engineer
Design Engineer & Senior Engineer

Design Engineer & Senior Engineer

Paignton Full-Time 43200 - 72000 £ / year (est.) No home office possible
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At a Glance

  • Tasks: Join us to design cutting-edge FPGA solutions for high-speed network cards.
  • Company: Be part of a dynamic startup focused on sustainable tech in the beautiful English Riviera.
  • Benefits: Enjoy flexible hybrid working, competitive salary, and bonuses up to 85%.
  • Why this job: Work with exciting technologies and a supportive team dedicated to innovation and sustainability.
  • Qualifications: Experience in FPGA design for 100Gbps networks and proficiency in Python/Tcl scripting required.
  • Other info: Opportunity to shape the future of technology while enjoying a vibrant work environment.

The predicted salary is between 43200 - 72000 £ per year.

Based in the English Riviera, this exciting new opportunity will join an established startup company to develop technologies for a sustainable future through ML and Datacentre technologies.

The experienced FPGA Design Engineer will be responsible for FPGA Design for the development of high-speed network interface cards. Key responsibilities will include:

  • Microarchitecture definition
  • RTL Implementation / synthesis/timing closure
  • Verification / Testing using SystemVerilog
  • Delivering & validating FPGA based lab setups for trials

Extensive hands-on industry experience of FPGA Design for network applications at 100Gbps and above.

Strong knowledge of FPGA tool flows (synthesis, partitioning, place & route, timing analysis).

Scripting in Python / Tcl.

The company offers an excellent salary, along with a bonus up to 85%, flexible and hybrid working, exciting technology and a great team working environment in new offices.

Design Engineer & Senior Engineer employer: Logik Source

Join a forward-thinking startup based in the stunning English Riviera, where innovation meets sustainability. As a Design Engineer or Senior Engineer, you'll thrive in a collaborative culture that values creativity and offers flexible hybrid working arrangements, alongside an attractive salary and bonus structure. With ample opportunities for professional growth and the chance to work on cutting-edge technologies, this is an ideal environment for those looking to make a meaningful impact in the field of FPGA design.
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Contact Detail:

Logik Source Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Design Engineer & Senior Engineer

✨Tip Number 1

Familiarise yourself with the latest FPGA design tools and technologies. Being well-versed in the specific tools mentioned in the job description, such as synthesis and timing analysis, will give you a competitive edge during discussions.

✨Tip Number 2

Showcase your hands-on experience with high-speed network applications. Prepare to discuss specific projects where you've successfully implemented FPGA designs for 100Gbps networks or above, as this will demonstrate your capability to meet their needs.

✨Tip Number 3

Brush up on your scripting skills in Python and Tcl. Be ready to share examples of how you've used these languages in previous projects, as this will highlight your versatility and problem-solving skills in FPGA design.

✨Tip Number 4

Research the company’s focus on sustainable technology and ML. Understanding their mission and values will allow you to align your answers during interviews, showing that you're not just a fit for the role but also for the company culture.

We think you need these skills to ace Design Engineer & Senior Engineer

FPGA Design
Microarchitecture Definition
RTL Implementation
Synthesis and Timing Closure
Verification and Testing using SystemVerilog
High-Speed Network Interface Cards Development
FPGA Tool Flows (Synthesis, Partitioning, Place & Route, Timing Analysis)
Scripting in Python
Scripting in Tcl
Lab Setup and Validation for FPGA Trials
Experience with 100Gbps Network Applications
Problem-Solving Skills
Attention to Detail
Team Collaboration
Adaptability to New Technologies

Some tips for your application 🫡

Tailor Your CV: Make sure your CV highlights your experience with FPGA design, particularly for high-speed network applications. Include specific projects or roles where you utilised relevant skills such as microarchitecture definition and RTL implementation.

Craft a Compelling Cover Letter: In your cover letter, express your passion for sustainable technology and how your background in FPGA design aligns with the company's mission. Mention your familiarity with tools like SystemVerilog and your scripting skills in Python or Tcl.

Showcase Relevant Projects: If you have worked on any projects involving 100Gbps network interface cards or similar technologies, be sure to detail these in your application. Highlight your role, the challenges faced, and the outcomes achieved.

Proofread Your Application: Before submitting, carefully proofread your application for any errors or typos. A polished application reflects your attention to detail, which is crucial for a design engineer role.

How to prepare for a job interview at Logik Source

✨Showcase Your FPGA Expertise

Be prepared to discuss your hands-on experience with FPGA design, especially for high-speed network applications. Highlight specific projects where you implemented microarchitecture and achieved timing closure, as this will demonstrate your technical proficiency.

✨Demonstrate Your Scripting Skills

Since scripting in Python and Tcl is essential for this role, be ready to provide examples of how you've used these languages in your previous work. Discuss any automation or optimisation tasks you've accomplished using scripts to enhance FPGA design processes.

✨Understand the Company’s Vision

Research the startup's focus on sustainable technologies and ML. Be prepared to articulate how your skills can contribute to their mission. Showing that you align with their values will make a positive impression.

✨Prepare for Technical Questions

Expect in-depth technical questions related to FPGA tool flows, such as synthesis, partitioning, and timing analysis. Brush up on these topics and be ready to solve problems on the spot, as this will showcase your analytical skills and expertise.

Design Engineer & Senior Engineer
Logik Source
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  • Design Engineer & Senior Engineer

    Paignton
    Full-Time
    43200 - 72000 £ / year (est.)

    Application deadline: 2027-05-16

  • L

    Logik Source

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