Senior Analog IC Layout Engineer
Senior Analog IC Layout Engineer

Senior Analog IC Layout Engineer

Reading Full-Time 48000 - 84000 £ / year (est.) No home office possible
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At a Glance

  • Tasks: Design and verify custom layouts for high-speed Analog circuits and IP.
  • Company: Join a leader in energy-efficient chip solutions based in Reading, UK.
  • Benefits: Work with cutting-edge technology and collaborate with a dynamic design team.
  • Why this job: Elevate your career by working on innovative projects in advanced semiconductor technologies.
  • Qualifications: Experience in custom Analog layout and EDA tools like Cadence Virtuoso is essential.
  • Other info: Contact Leon Morrison at IC Resources for more details.

The predicted salary is between 48000 - 84000 £ per year.

This is an opportunity for an experienced Senior Analog IC Layout Engineer to work for an established leader in energy efficient chip solutions. Based in Reading, UK, the Senior Analog IC Layout Engineer will be responsible for custom layout and verification of Analog circuits, cells, blocks, and IP for multi-Gigabit high speed SerDes up to and beyond 28Gb/s and/or memory IO in advanced semiconductor technology nodes.

Other responsibilities include:

  1. Layout and verification of high-speed Analog circuits
  2. Working closely with the design team to understand requirements and implement solutions
  3. Support IP and chip level integration
  4. Interact with customers on requirements and IP delivery
  5. Exposure to flip-chip package technologies

Experience is required in some or all of the following:

  1. Custom Analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or high frequency circuits
  2. Layout of high-speed or high frequency circuits such as:
    • Amplifiers
    • Oscillators
    • Phase-locked loops
    • Delay-locked loops
    • Biasing
    • Buffers
    • Regulators
    • Filters
    • Data converters
  3. Layout approaches and techniques for high-speed circuits, matching constraints, minimisation of parasitics, power grids, and ESD requirements
  4. Modern semiconductor process technologies including 28nm, 14/16nm, 7nm
  5. EDA tools for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc.

Take the next step in your career—contact Leon Morrison at IC Resources today:

Phone: +44 (0)208 400 2483

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Senior Analog IC Layout Engineer employer: IC Resources

Join a pioneering leader in energy-efficient chip solutions as a Senior Analog IC Layout Engineer in Reading, UK, where innovation meets collaboration. Our vibrant work culture fosters creativity and teamwork, providing ample opportunities for professional growth and development in advanced semiconductor technologies. Enjoy competitive benefits and the chance to work on cutting-edge projects that make a real impact in the industry.
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Contact Detail:

IC Resources Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Senior Analog IC Layout Engineer

✨Tip Number 1

Make sure to showcase your experience with high-speed Analog circuits in your conversations. Highlight specific projects where you successfully implemented solutions for multi-Gigabit data-link transceivers or high-frequency circuits.

✨Tip Number 2

Familiarize yourself with the latest semiconductor process technologies, especially 28nm, 14/16nm, and 7nm. Being able to discuss these technologies confidently will demonstrate your up-to-date knowledge and relevance in the field.

✨Tip Number 3

Prepare to discuss your proficiency with EDA tools like Cadence Virtuoso and Spectre/HSpice. Be ready to provide examples of how you've used these tools for design and verification in past projects.

✨Tip Number 4

Engage with the design team during discussions to show your collaborative spirit. Emphasizing your ability to work closely with others to understand requirements and deliver results can set you apart from other candidates.

We think you need these skills to ace Senior Analog IC Layout Engineer

Custom Analog Layout Design
High-Speed Circuit Design
Verification of Analog Circuits
Multi-Gigabit SerDes
Layout Techniques for High-Speed Circuits
Understanding of Parasitics Minimization
Power Grid Design
ESD Requirements Knowledge
Experience with 28nm, 14/16nm, 7nm Technologies
Proficiency in EDA Tools (Cadence Virtuoso, Spectre/HSpice, Calibre/PVS)
DRC/LVS Verification
Parasitics Extraction and Modelling
EM and IR Drop Analysis
Customer Interaction Skills
Collaboration with Design Teams

Some tips for your application 🫡

Understand the Role: Make sure to thoroughly read the job description for the Senior Analog IC Layout Engineer position. Understand the key responsibilities and required skills, especially in custom layout and verification of Analog circuits.

Highlight Relevant Experience: In your CV and cover letter, emphasize your experience with high-speed Analog circuits, particularly any work with multi-Gigabit serial data-link transceivers or high frequency circuits. Mention specific projects or technologies you've worked with.

Showcase Technical Skills: Detail your proficiency with EDA tools like Cadence Virtuoso and Spectre/HSpice. Include any experience with modern semiconductor process technologies such as 28nm, 14/16nm, and 7nm, as well as your familiarity with layout techniques and constraints.

Tailor Your Application: Customize your application materials to reflect the specific requirements mentioned in the job description. Use keywords from the listing to demonstrate that you are a perfect fit for the role.

How to prepare for a job interview at IC Resources

✨Showcase Your Technical Expertise

Be prepared to discuss your experience with custom Analog layout and verification. Highlight specific projects where you worked on multi-Gigabit high-speed SerDes or memory IO, and be ready to explain the challenges you faced and how you overcame them.

✨Understand the Design Requirements

Demonstrate your ability to work closely with design teams by discussing how you gather and implement requirements. Share examples of how you have successfully collaborated with others to deliver IP and chip-level integration.

✨Familiarize Yourself with EDA Tools

Make sure you are well-versed in the EDA tools mentioned in the job description, such as Cadence Virtuoso and Spectre. Be ready to discuss how you have used these tools for design and verification, including DRC/LVS checks and parasitics extraction.

✨Discuss Your Knowledge of Modern Semiconductor Technologies

Prepare to talk about your experience with modern semiconductor process technologies, especially 28nm, 14/16nm, and 7nm nodes. Highlight any relevant projects and how you addressed challenges related to power grids, ESD requirements, and minimization of parasitics.

Senior Analog IC Layout Engineer
IC Resources
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  • Senior Analog IC Layout Engineer

    Reading
    Full-Time
    48000 - 84000 £ / year (est.)

    Application deadline: 2027-01-26

  • I

    IC Resources

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