Senior Engineer, Design Verification Engineering

Verification Engineer Bristol and/or fully remote within the United Kingdom. £AI Neuromorphic Silicon chips I am seeking a Digital Verification Engineer to join a dynamic fabless semiconductor team. You will be part of a wider group that will include Digital, Analog and BE Engineers and work on the development of AI neuromorphic chips. You will be responsible for the design, simulation and verification of digital block implemented in RTL for various functions including control state machine DSP, and multiple clock domain interface management. Their technology provides fast and easy conversion of trained Neural Networks into miniscule AI silicon chips with ultra-low power consumption, low latency and small size. Work with backend/implementation teams to address synthesis, timing, DFT issues for ASIC implementation. Define verification and test plan, run regressions, reproduce, and debug functional and performance bugs. Analyze circuit for failure root cause analysis, investigate anomalous observations in silicon across various conditions, including PVT variations, and propose solutions. RTL design/verification of digital circuits in Verilog. Define verification and test plan, run regressions, reproduce, and debug functional and performance bugs. Proficiency with EDA tools (Candence, Mentor) and design languages including Verilog and systemVerilog Understanding of synthesis, static timing analysis, and netlist verifications