Formal Verification Engineers (x4) - Oxfordshire -Permanent

Formal Verification Engineers (x4)

Industry: Semiconductors

Type of contract: Permanent

Location: Oxfordshire

Work setting: 4-5 days in office

Responsibilities:

• Mentorship from Principal & Distinguished Engineers.
• Opportunity to mentor colleagues.
• Gain insight into various stages of the design & verification cycle.
• Hands-on experience with leading-edge EDA tools and advanced process nodes, using industry-standard languages and methodologies (e.g., SystemVerilog, UVM, Formal).
• Work on high-volume data center & enterprise products used by leading industry companies.
• Collaborate on projects with our client\’s teams worldwide.
• Plan and manage resource utilization per project.
• Contribute to the verification strategy.
• Own task breakdowns and time estimations.
• Utilize a metric-driven mindset to deliver high-quality, measurable results within schedule.

Requirements:

• Bachelor’s or Master’s degree in Electronic Engineering, Computer Engineering, or related field
• 10+ years of experience in digital ASIC verification, with a strong focus on Formal Verification
• Expertise in Formal Verification methodologies, including: o Property Checking & Assertion-Based Verification (ABV) o Formal Test Planning & Coverage Analysis o Formal Sign-Off & Proof Convergence Strategies
• Hands-on experience with industry-standard formal tools, such as: o Cadence JasperGold o Synopsys VC Formal o Siemens Questa Formal
• Strong SystemVerilog Assertions (SVA) & PSL (Property Specification Language) knowledge
• Ability to translate architecture and design specifications into formal properties and constraints
• Familiarity with debugging inconclusive proofs and optimizing proof convergence
• Experience in verifying complex protocols (e.g., PCIe, NVMe, DDR, AMBA) using formal methods
• Proficiency in scripting for automation (Python, Perl, TCL)
• Strong analytical, problem-solving, and debugging skills in a formal verification context
• Team player with strong verbal and written communication skills

Desirable Skills:

• Experience integrating Formal Verification into a larger verification strategy (hybrid formal + simulation approaches)
• Familiarity with Equivalence Checking methodologies
• Exposure to UVM-based verification, but primary focus on Formal
• Knowledge of storage or networking protocols (e.g., SAS, SATA, NVMe, Ethernet)
• Experience with Atlassian toolchain (JIRA, Confluence, BitBucket, EazyBI)
• Experience setting up and maintaining Jenkins-based verification flows
• Japanese language proficiency (optional, if applicable)

Salary & Benefits

• Up to 120k basic + up to 20% bonus
• Electric car scheme
• Generous pension plan & health care plan
• 25 days holiday
• Employee assistance
• Additional holiday for 5 years of service
• Relocation package offered