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- Tasks: Join us as a Design Verification Engineer, creating and executing verification plans and test cases.
- Company: Be part of an innovative tech company pushing the boundaries of design verification in SoCs.
- Benefits: Enjoy flexible working hours, remote work options, and a vibrant team culture.
- Why this job: This role offers hands-on experience with cutting-edge technology and a chance to make a real impact.
- Qualifications: Ideal candidates should have knowledge of UVM, Verilog/System Verilog, and a passion for problem-solving.
- Other info: Opportunity to work on exciting projects and collaborate with industry experts.
The predicted salary is between 36000 - 60000 £ per year.
An excellent opportunity has arisen to join a global leader in advanced semiconductor technologies. This role offers the chance to work on cutting-edge 5nm designs, supporting the latest PCIe interfaces, protocols, and NAND flash solutions. Visa can be considered for experienced engineers with the right skills. As a Verification Engineer, you will join an industry-leading SoC development team tackling complex design challenges including high-speed interfaces, high-performance accelerators, and multi-CPU architectures. Team responsibilities span SoC architecture, RTL design, verification, synthesis, FPGA prototyping, and validation. Essential qualifications and skillsBachelor’s or Master’s degree in Electronic Engineering (or related field)Experience in digital ASIC design and verification, including:Defining functional requirements for verification environments & metricsSystemVerilog UVM testbenchesFormal proof verificationUnderstanding of C test cases and C codeScripting languages (e.g. Python, Perl, TCL) Desirable skillsExperience with formal verification tools (JasperGold, VC Formal)Familiarity with C/C++ developmentPrior SSD experience with storage interfaces such as SAS or PCIe (NVMe preferred)
Contact Detail:
LinkedIn Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Design Verification Engineer
✨Tip Number 1
Familiarise yourself with UVM (Universal Verification Methodology) as it's a key requirement for this role. Consider working on personal projects or contributing to open-source projects that utilise UVM to showcase your practical experience.
✨Tip Number 2
Brush up on your knowledge of CPU connectivity and the GNU toolchain. Understanding how to verify CPU connections to IP blocks will give you an edge, so try to get hands-on experience with relevant tools and techniques.
✨Tip Number 3
Develop a strong understanding of coverage-driven verification. Being able to create effective verification plans and identify coverage gaps will be crucial, so consider studying existing methodologies and best practices in this area.
✨Tip Number 4
Network with professionals in the field of design verification. Attend industry meetups or online forums where you can discuss challenges and solutions with others, which can provide insights and potentially lead to job referrals.
We think you need these skills to ace Design Verification Engineer
Some tips for your application 🫡
Understand the Role: Before applying, make sure you fully understand the responsibilities of a Design Verification Engineer. Familiarise yourself with terms like UVM, RTL, and coverage-driven verification to demonstrate your knowledge in your application.
Tailor Your CV: Highlight relevant experience in design verification, particularly with UVM and testbench development. Include specific projects where you've created verification plans or debugged test failures to showcase your skills.
Craft a Strong Cover Letter: In your cover letter, explain why you're passionate about design verification and how your background aligns with the job requirements. Mention any specific methodologies or tools you've used that are relevant to the position.
Showcase Your Technical Skills: Be sure to mention your proficiency with tools like the GNU toolchain and your experience with writing test cases in Verilog/System Verilog. Providing examples of past projects can help illustrate your capabilities.
How to prepare for a job interview at LinkedIn
✨Understand the Verification Process
Make sure you have a solid grasp of the design verification process, especially coverage-driven verification. Be prepared to discuss how you would create a verification plan document and the importance of each step in the process.
✨Familiarise Yourself with UVM
Since the role involves creating a UVM verification environment, brush up on your knowledge of UVM methodologies. Be ready to explain how you've used UVM in past projects and how it can enhance the verification process.
✨Showcase Your Debugging Skills
Debugging test failures is a key part of the job. Prepare examples from your experience where you successfully identified and resolved issues in test cases or regressions, highlighting your analytical skills and attention to detail.
✨Discuss Coverage Requirements
Be prepared to talk about how you would develop tests to meet functional and code coverage requirements. Discuss any tools or techniques you've used to analyse coverage gaps and how you ensured all design blocks were thoroughly verified.
